Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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10 May 2009
TL;DR: This work introduces an automated debug technique that provides the user with both spatial and temporal information about the source of error, based on a Partial MaxSAT formulation which models errors at the CNF clause level instead of the traditional gate or module level.
Abstract: Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying possible error sources in the design. Unfortunately, these techniques do not provide any information regarding the time at which the bug is active during an error trace or counter-example. This work introduces an automated debug technique that provides the user with both spatial and temporal information about the source of error. The proposed method is based on a Partial MaxSAT formulation which models errors at the CNF clause level instead of the traditional gate or module level. Thus, error sites are identified based on erroneous implications that correspond to locations both in the design and in the error trace. Experiments demonstrate that we can provide this additional information at no extra cost in run time and are able to prune about 61% of all simulation time frames from the debugging process. When compared to a trivial formulation we observe a performance improvement of up to two orders of magnitude and 5× on average when using the proposed formulation.
28 citations
18 Nov 2002
TL;DR: Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%.
Abstract: The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.
28 citations
TL;DR: This ATPG algorithm is based on Boolean Satisfiability (SAT) and utilizes the stuck-at fault model for representing signaling faults and a weighted partial Max-SAT formulation is used to enable efficient selection of the most effective drug.
Abstract: Cancer and other gene related diseases are usually caused by a failure in the signaling pathway between genes and cells. These failures can occur in different areas of the gene regulatory network, but can be abstracted as faults in the regulatory function. For effective cancer treatment, it is imperative to identify faults and select appropriate drugs to treat the faults. In this paper, we present an extensible Max-SAT based automatic test pattern generation (ATPG) algorithm for cancer therapy. This ATPG algorithm is based on Boolean Satisfiability (SAT) and utilizes the stuck-at fault model for representing signaling faults. A weighted partial Max-SAT formulation is used to enable efficient selection of the most effective drug. Several usage cases are presented for fault identification and drug selection. These cases include the identification of testable faults, optimal drug selection for single/multiple known faults, and optimal drug selection for overall fault coverage. Experimental results on growth factor (GF) signaling pathways demonstrate that our algorithm is flexible, and can yield an exact solution for each feature in much less than 1 second.
28 citations
Cites methods from "Digital Systems Testing and Testabl..."
...There are several methods for performing sequential ATPG, the most common of which is Time-Frame expansion [17]....
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03 Jan 2006
TL;DR: This work first proposes several techniques to analyze the relationship of logic failure locations and collapse multiple logic fail locations into single defects, and then uses a minimum set covering algorithm to find final diagnosis candidates.
Abstract: The general flow of location based logic diagnosis begins with finding a set of locations which can explain one or more single location at-a time (SLAT) failing patterns [Bartenstein, 2001], then a heuristic method is used to find subsets of locations which can explain all the SLAT failing patterns are determined as the results of logic diagnosis. However, since the observed test fails may correspond to logic failures from multiple locations, the existing heuristics may find incomplete or wrong locations of the defect due to the ignorance of the correlation between the logic failure locations and the defect. In this work, we first propose several techniques to analyze the relationship of logic failure locations and collapse multiple logic failure locations into single defects, and then use a minimum set covering algorithm to find final diagnosis candidates. In this way, we can not only identify defect type but also improve diagnosis accuracy and resolution. Experimental results on both simulated defects and silicon defects are given to demonstrate effectiveness of the proposed method.
28 citations
Cites background from "Digital Systems Testing and Testabl..."
...In this way, we can not only identify defect type but also improve diagnosis accuracy and resolution....
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TL;DR: A testability measure is proposed to guide test pattern generation and produce patterns with few care bits that can effectively reduce the amount of test data that needs to be stored on-chip.
Abstract: We present a new scan-based built-in self-test (BIST) technique, which is based on weighted scan-enable signals and a reconfigurable scan-forest architecture. A testability measure is proposed to guide test pattern generation and produce patterns with few care bits. This approach can effectively reduce the amount of test data that needs to be stored on-chip. The proposed BIST method relies on the pseudorandom and deterministic phases. The scan-forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that a linear feedback shift register, with size equal to the maximum number of the care bits in the deterministic patterns for the random-resistant faults, is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method for single stuck-at faults. In addition, experimental results show that the patterns applied to the circuit under test provide more n-detection than those applied by a traditional scan-chain architecture with a single test session.
28 citations
Additional excerpts
...Index Terms—Deterministic built-in self-test (BIST), scanbased BIST, scan forest, weighted scan-enable signals....
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