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Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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Proceedings Article•DOI•
05 Nov 2006
TL;DR: Improved on state-of-the-art combinational equivalence checking based on Boolean satisfiability by using more intelligent simulation, using CNF-based SAT with circuit-based decision heuristics, and interleaving SAT with low-effort logic synthesis.
Abstract: The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output (i.e. proving equivalence of the output to constant 0). This paper improves on this method by (a) using more intelligent simulation, (b) using CNF-based SAT with circuit-based decision heuristics, and (c) interleaving SAT with low-effort logic synthesis. Experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. In several cases, the new solver succeeded in solving previously unsolved problems.

144 citations

Journal Article•DOI•
TL;DR: A gate-level transient fault simulation environment which has been developed based on realistic fault models and can be used for any transient fault which can be modeled as a transient pulse of some width is described.
Abstract: Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

140 citations

Proceedings Article•DOI•
30 Sep 2003
TL;DR: X-tolerant deterministic BIST (XDBIST), a novel method to efficiently compress and apply scan pattems generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture, is presented.
Abstract: We present X-tolerant deterministic BIST (XDBIST), a novel method to efficiently compress and apply scan pattems generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. Our method allows test patterns to have any number of unknown values with no degradation in compression and application efficiency. XDBIST does not require changing the core logic of the device under test (DUT); no test points or X-blockage logic need be inserted. The proposed solution guarantees the same high test coverage and diagnosis ability as deterministic scan-ATPG and uses the same tester flow, while reducing test data volume and tester cycles by more than 10 times.

134 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...Scan has long been the fundamental design-for-test (DFT) method to control test cost [2], [3]....

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Proceedings Article•DOI•
28 May 2008
TL;DR: An overview of some of the most well-known applications of SAT and a brief survey of recent work on extensions of SAT, including pseudo-Boolean constraints, maximum satisfiability, model counting and quantified Boolean formulas are provided.
Abstract: Boolean satisfiability (SAT) solvers have been the subject of remarkable improvements since the mid 90s. One of the main reasons for these improvements has been the wide range of practical applications of SAT. Indeed, examples of modern applications of SAT range from termination analysis in term-rewrite systems to circuit-level prediction of crosstalk noise. The success of SAT solvers motivated many practical applications, but many practical applications have also provided the examples and the challenges that allowed the development of more efficient SAT solvers. This paper provides an overview of some of the most well-known applications of SAT and outlines several other successful applications of SAT. Moreover, the improvements in SAT solvers motivated the development of new algorithms for strategic extensions of SAT. As a result, the paper also provides a brief survey of recent work on extensions of SAT, including pseudo-Boolean constraints, maximum satisfiability, model counting and quantified Boolean formulas.

134 citations


Cites background or methods from "Digital Systems Testing and Testabl..."

  • ...In what follows combinational circuits are assumed, but the same ideas can be extended to sequential circuits [2]....

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  • ...The most widely used approach for identifying fabrication defects is automatictestpattern generation (ATPG) [2]....

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  • ...Additional improvements were further proposed in [39], including the reuse of learnt clauses in between target faults and the encoding of conditions for unique sensitization points [2]....

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Proceedings Article•DOI•
28 Sep 1999
TL;DR: Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease the heat dissipated during BIST by significant amounts while attaining high fault coverage, especially for circuits with moderate to large number of scan inputs.
Abstract: A new BIST TPG design, called low-transition random TPG (LT-RTPG), that is comprised of an LFSR, a k-input AND gate, and a T flip-flop, is presented. When used to generate test patterns for test-per-scan BIST, it decreases the number of transitions that occur during scan shifting and hence decreases the heat dissipated during testing. Various properties of LT-RTPGs are studied and a methodology for their design is presented. Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease the heat dissipated during BIST by significant amounts while attaining high fault coverage, especially for circuits with moderate to large number of scan inputs.

131 citations