Digital Systems Testing and Testable Design
Citations
26 citations
Cites background from "Digital Systems Testing and Testabl..."
...In recent years, many competitive solutions have been proposed, most of which based on heuristic approaches [1] [5] [6] [8] [10] [11] [12] [13] [14] [15]....
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26 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...These ambiguity groups, which were taken from Abramovici et al. (1990) are listed in Table 1....
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...For illustration purposes, we use a simple digital circuit (Abramovici, Breuer, and Friedman, 1990)....
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...Finally, Abramovici et al. (1990) note that the nearest neighbor approach to matching inexact patterns in the dictionary, while effective in many cases, “is not guaranteed to produce the correct diagnosis.”...
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26 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...Given a set of vectors V for which a circuit (or netlist) C demonstrates an incorrect behavior, the objective of design debugging is to nd the gates that may be responsible for this incorrect behavior [ 5 ]....
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...Currently, automated design debugging approaches are based on simulation, symbolic, or constraint satisfaction techniques [ 5 ], [6], [7]....
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26 citations
Cites background or methods or result from "Digital Systems Testing and Testabl..."
...In order to avoid the wakeup of empty entries placed in turned on banks, we assume that the wakeup is gated in each individual entry that is empty [8]....
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...As previous works [8][6], no compaction mechanism for the issue queue has been assumed since compaction results in a significant amount of extra energy consumption....
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...It has been reported in previous studies of web servers [3], proxy servers [8] and World Cup ’98 Characterization [2] that mean and median document transfer sizes are quite small, fewer than 13K and 3K bytes respectively....
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...We compare this scheme with the approach in [8], and show that the proposed technique provides significant advantages....
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...Section 3 describes the proposed technique and the mechanism proposed in [8], which is used for comparison purposes....
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26 citations
Cites background or methods from "Digital Systems Testing and Testabl..."
...3) Modeling Sequential Circuits: Every sequential circuit can be represented by the conventional Huffman model [ 3 ]....
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...Previous work reported in the literature for the DBFTG may be broadly classified into two, namely, the conventional automatic test pattern generation (ATPG) [ 3 ]-based approaches and the constraint-based approaches....
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...Classical ATPG methods [ 3 ] work at gate-level representations of the design and hence exhibit less scalability with increasing design size....
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...The behavior of a sequential circuit over time frames can be modeled as a combinational circuit using the conventional time frame expansion approach, which unrolls the combinational part of , times [ 3 ]....
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...The previous technique is efficient only for circuit models in which: 1) the data and control paths are separate and 2) have design for testability (DFT) [ 3 ] support....
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