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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
A partial scan methodology for testing self-timed circuits
A. Khoche,Erik Brunvand +1 more
TL;DR: This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults that offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage.
Journal ArticleDOI
An efficient test relaxation technique for synchronous sequential circuits
TL;DR: This paper proposes an efficient test-relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.
Book ChapterDOI
Approximate Symbolic Model Checking for Incomplete Designs
Tobias Nopper,Christoph Scholl +1 more
TL;DR: This work considers the problem of checking whether an incomplete design can still be extended to a complete design satisfying a given CTL formula and whether the property is satisfied for all possible extensions.
Proceedings ArticleDOI
Fault behavior dictionary for simulation of device-level transients
TL;DR: In this article, the authors present a methodology for the simulation of massive number of device-level transient faults and evaluate the fault injection locations and the gate around those locations with SPICE.
Journal ArticleDOI
Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors
Hyungjun Kim,Siva Bhanu Krishna Boga,Arseniy Vitkovskiy,Stavros Hadjitheophanous,Paul V. Gratz,Vassos Soteriou,Maria K. Michael +6 more
TL;DR: A key finding of this modeling is that, counter to prevailing wisdom, wearout in the CMP's on-chip interconnect is correlated with lack of load observed in the NoC routers rather than high load, and a novel wearout-decelerating scheme is developed, which yields an ∼2,300× decrease in the rate of wear.