Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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TL;DR: I/sub DDQ/ testing is a well accepted testing approach based on the observation of the quiescent current consumption, but its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.
Abstract: I/sub DDQ/ testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which escape other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.
25 citations
Cites methods from "Digital Systems Testing and Testabl..."
...For the last two decades, much effort has been devoted to provide solutions to these limitations by using design for testability (DFT) techniques, built-in self test (BIST) and complementary testing methods using other chip observables such as delay [ 3 ] or current consumption [4]‐[12]....
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22 Jun 2001
TL;DR: The design and evaluation of an 8-bit adiabatic multiplier has been presented and correct chip operation has been validated for operating frequencies up to 130MHz, the limit of the experimental setup.
Abstract: This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130 pJ per operation at 200 MHz. Our 11,854-transistor chip has been fabricated in a 0.5 /spl mu/m standard CMOS process with an active area of 0.470 mm/sup 2/. Correct chip operation has been validated for operating frequencies up to 130 MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.
25 citations
16 Mar 1992
TL;DR: Methods for test-data compression ensuring zero aliasing in logic circuits are described and experimental results are presented to support the practicality of the methods proposed in ensuring zero Aliasing.
Abstract: Methods for test-data compression ensuring zero aliasing in logic circuits are described. Aliasing occurs when due to loss of information during compression of the output response, a faulty circuit appears to be fault free. Zero aliasing is guaranteed for a given set of target faults, detected by the test set applied to the circuit. The inability of probabilistic analysis of aliasing to predict coverage of target faults is thus alleviated. Experimental results are presented to support the practicality of the methods proposed in ensuring zero aliasing. >
25 citations
20 Sep 1992
TL;DR: It is shown that even when a sequential test generator does a "perfect" job and achieves 100% detectable fault coverage, a circuit passing the test may still exhibit severe testability problems caused by undetectable faults that prevent initialization (FPIs).
Abstract: In this gaper we show that even when a sequential test generator does a "perfect" job and achieves 100% detectable fault coverage, a circuit passing the test may still exhibit severe testability problems caused by undetectable faults that prevent initialization (FPIs). Thus 100% fault coverage may be a misleading quality indicator, unless undetectable FPIs are accounted for. We present the first algorithm able to identify undetectable FPIs and we report the results obtained for the sequential benchmark circuits. We also discuss the design for testability techniques that make these faults detectable.
25 citations
TL;DR: It is shown that any moment of test length requires knowledge of all the moments of fault coverage, and hence, its pmf, and that estimates of variances can be used to bound average test length quite effectively.
Abstract: Fault coverage and test length estimation in circuits under random test is the subject of this paper. Testing by a sequence of random input patterns is viewed as sequential sampling of faults from a given fault universe. Based on this model, the probability mass function (pmf) of fault coverage and expressions for all its moments are derived. This provides a means for computing estimates of fault coverage as well as determining the accuracy of the estimates. Test length, viewed as waiting time on fault coverage, is analyzed next. We derive expressions for its pmf and its probability generating function (pgf). This allows computation of all the higher order moments. In particular, expressions for mean and variance of test length for any specified fault coverage are derived. This is a considerable enhancement of the state of the art in techniques for predicting test length as a function of fault coverage. It is shown that any moment of test length requires knowledge of all the moments of fault coverage, and hence, its pmf. For this reason, expressions for approximating its expected value and variance, for user specified error bounds, are also given. A methodology based on these results is outlined. Experiments carried out on several circuits demonstrate that this technique is capable of providing excellent predictions of test length. Furthermore it is shown, as with fault coverage prediction, that estimates of variances can be used to bound average test length quite effectively. >
25 citations