Book•
Digital Systems Testing and Testable Design
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
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16 Apr 2007
TL;DR: Fault masking for crossbar-based nanoelectronics PLAs is investigated and a class of fault masking approaches exploiting logic tautology in two-level PLAs are presented to enhance the reliability of nanoelection PLAs significantly at low hardware cost.
Abstract: A regular structure and capability to implement arbitrary logic functions in a two-level logic form have placed crossbar-based programmable logic arrays (PLAs) as promising implementation architectures in the emerging nanoelectronics environment. Yet reliability constitutes an important concern in the nanoelectronics environment, necessitating a thorough investigation and its effective augmentation for crossbar-based PLAs. We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs. Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars. Based on this observation, we present a class of fault masking approaches exploiting logic tautology in two-level PLAs. The proposed approaches enhance the reliability of nanoelectronics PLAs significantly at low hardware cost
25 citations
Cites methods from "Digital Systems Testing and Testabl..."
...Fault models for PLAs have been developed early in the research history of PLA testing methodologies [ 19 ]....
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18 Jan 2005
TL;DR: Best was the strategy of merging logic blocks with adjacent gates on the only path from the block output to the primary output, with a resulting speedup of up to 16x for CNF formulas with hundreds of thousands of variables, millions of clauses, and tens of millions of literals.
Abstract: Compared are seven schemes for encoding unobservability of logic blocks in Boolean-to-CNF translation. Four of the schemes are based on merging of logic blocks with adjacent gates toward the primary output. Two are based on using CNF unobservability variables to encode the unobservability of logic blocks. Also explored is a hybrid scheme. Encoding the unobservability of logic blocks accelerated the SAT-solving of Boolean formulas from formal verification of complex micro-processors, while allowing us to use a conventional CNF-based SAT-solver. On unsatisfiable CNF formulas, best was the strategy of merging logic blocks with adjacent gates on the only path from the block output to the primary output, with a resulting speedup of up to 16x for CNF formulas with hundreds of thousands of variables, millions of clauses, and tens of millions of literals. Furthermore, the speedup is relative to an already very efficient Boolean-to-CNF translation. On satisfiable CNF formulas, best was the strategy of merging logic blocks with leaf gates and with adjacent gates on the only path to the primary output, as well as exploiting the polarity of gates and logic blocks to reduce the number of their clauses. The presented optimizations are general and applicable to other classes of Boolean formulas.
25 citations
Cites background from "Digital Systems Testing and Testabl..."
...However, this translation captures only local structural information for each gate, and so does not exploit the concept of observability don’t-cares [7][27] (related to the concept of dominators in testing [1])—that the output values of subcircuits may be unobservable at the main output, i....
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01 May 1998
TL;DR: Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with this scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5 %).
Abstract: This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST) The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques Finally a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed an the circuit Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 64% (25 %)
25 citations
Cites background from "Digital Systems Testing and Testabl..."
...This can be done with the help of some test points, i.e., extra control/observe points [ 2 ]....
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...Du et oth eincreasin gcomplexit yo fintegrate dcircuits ,BIS Tis emergin ga s apopula rtestin gtechniqu efo rlarg ean dcomple xdesigns .BIS Tha ssevera ladvantage sove rothe rtes tapproache s[1], [ 2 ] ,e.g....
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TL;DR: A BIST-based test methodology is presented that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips and the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.
Abstract: As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.
25 citations
Cites background from "Digital Systems Testing and Testabl..."
...The ORA (output response analyzer) circuit observes the outputs and analyzes their validity [ 27 ]....
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26 Oct 1991
TL;DR: In this article, the propagation characteristics of a module are represented by structures called ambiguity sets, which can be used for hierarchical test generation and design for testability, and also to aid in designing circuits suitable for high-level test generation.
Abstract: Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.
25 citations