scispace - formally typeset
Search or ask a question
Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Citations
More filters
Posted Content
TL;DR: In this paper, a mapping between initial states of the Fibonacci and the Galois configurations of NLFSRs is established, and it is shown how to choose initial states for two configurations so that the resulting output sequences are equivalent.
Abstract: In this paper, a mapping between initial states of the Fibonacci and the Galois configurations of NLFSRs is established. We show how to choose initial states for two configurations so that the resulting output sequences are equivalent.

25 citations

Journal ArticleDOI
TL;DR: This work has shown that stochastic computational modeling can aid in the design of scientifically well-grounded targeted therapies that can be employed for the treatment of prostate cancer patients.
Abstract: Prostate cancer is one of the most prevalent cancers in males in the United States and amongst the leading causes of cancer related deaths. A particularly virulent form of this disease is castration-resistant prostate cancer (CRPC), where patients no longer respond to medical or surgical castration. CRPC is a complex, multifaceted and heterogeneous malady with limited standard treatment options. The growth and progression of prostate cancer is a complicated process that involves multiple pathways. The signaling network comprising the integral constituents of the signature pathways involved in the development and progression of prostate cancer is modeled as a combinatorial circuit. The failures in the gene regulatory network that lead to cancer are abstracted as faults in the equivalent circuit and the Boolean circuit model is then used to design therapies tailored to counteract the effect of each molecular abnormality and to propose potentially efficacious combinatorial therapy regimens. Furthermore, stochastic computational modeling is utilized to identify potentially vulnerable components in the network that may serve as viable candidates for drug development. The results presented herein can aid in the design of scientifically well-grounded targeted therapies that can be employed for the treatment of prostate cancer patients.

25 citations


Cites background from "Digital Systems Testing and Testabl..."

  • ...These abnormalities in the signaling network can be represented as stuck-at faults [26]....

    [...]

Proceedings ArticleDOI
19 Jul 1998
TL;DR: Systematic Testing of Robustness by Examination of Selected Scenarios (STRESS) aims to cut the time and effort needed to explore pathological cases of a protocol during its design and demonstrate how effective systematic simulation can be in studying protocol robustness.
Abstract: We propose a method for using simulation to analyze the robustness of multiparty (multicast-based) protocols in a systematic fashion. We call our method Systematic Testing of Robustness by Examination of Selected Scenarios (STRESS). STRESS aims to cut the time and effort needed to explore pathological cases of a protocol during its design. This paper has two goals: (1) to describe the method, and (2) to serve as a case study of robustness analysis of multicast routing protocols. We aim to offer design tools similar to those used in CAD and VLSI design, and demonstrate how effective systematic simulation can be in studying protocol robustness.

25 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...BIST uses a ‘test generator’ to produce the input patterns applied to the circuit under test, and ‘response monitor circuit’ to monitor and detect error signals....

    [...]

  • ...There is an analogy between STRESS and VLSI systematic design for testability using Built-In-Self-Test (BIST) [1]....

    [...]

  • ...BIST provides a systematic technique for chip testing synthesis, and can be used to detect faults due to single-stuck-line....

    [...]

Journal ArticleDOI
TL;DR: Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault Coverage or very close to complete fault coverage.
Abstract: The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

25 citations


Cites methods from "Digital Systems Testing and Testabl..."

  • ...SCAN-BASED BIST can be simply classified into two types: test-per-scan and test-per-clock [1], [2], [5] test schemes....

    [...]

Book ChapterDOI
22 May 2006
TL;DR: This paper provides a tutorial on various SAT-based verification methods developed for verifying large hardware designs, focusing separately on methods for finding bugs and for finding proofs for correctness properties.
Abstract: Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods. This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.

24 citations