Dogleg Channel Routing is NP-Complete
01 Jan 1985-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 4, Iss: 1, pp 31-41
TL;DR: It is shown that an efficient optimal algorithm for interconnecting two rows of points across an intervening channel is unlikely to exist by establishing that this problem is NP-complete.
Abstract: Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algorithm has yet been discovered for the general case problem. We show that such an algorithm is unlikely to exist by establishing that this problem is NP-complete.
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Book•
31 Jan 1993
TL;DR: This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.
Abstract: From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.
927 citations
TL;DR: This is the fourteenth edition of a quarterly column that provides continuing coverage of new developments in the theory of NP-completeness, and readers who have results they would like mentioned (NP-hardness, PSPACE- hardness, polynomialtime-solvability, etc.), or open problems they wouldlike publicized, should send them to David S. Johnson.
857 citations
Book•
11 Mar 2009TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
Abstract: This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.
Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
Table of Contents
Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.
200 citations
01 Dec 1985
TL;DR: These algorithms subsume most of the polynomial-time algorithms in the literature for planar routing and routability testing in the rectilinear grid model and provide an explicit construction of a database to support computation involving the layout topology.
Abstract: This paper studies the problem of routing wires in a grid among features on one layer of a VLSI chip, when a sketch of the layer is given. A sketch specifies the positions of features and the topology of the interconnecting wires. We give polynomial-time algorithms that (1) determine the routability of a sketch, and (2) produce a routing of a sketch that optimizes both individual and total wire length. These algorithms subsume most of the polynomial-time algorithms in the literature for planar routing and routability testing in the rectilinear grid model. We also provide an explicit construction of a database, called the rubber-band equivalent, to support computation involving the layout topology.
173 citations
TL;DR: YACR2 is a channel router that minimizes the number of through vias in addition to the area used to complete the routing in a two-layer channel.
Abstract: YACR2 is a channel router that minimizes the number of through vias in addition to the area used to complete the routing in a two-layer channel. It can route channels with cyclic constraints and uses a virtual grid. YACR2 uses preferably one layer for the horizontal segments of the nets and the other for the vertical ones but it may require the routing of a few horizontal segments in the second layer. Experimentally YACR2 performs better than any of the channel routers proposed thus far both in terms of area used and through vias. It routed the Deutsch Difficult Example in density with substantially less vias than Burstein's hierarchical router and with the default parameter values in less than 3 s of CPU time on a VAX 11/780.
161 citations
References
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28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
655 citations
28 Jun 1976
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Abstract: This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.
364 citations
23 Jun 1980
TL;DR: This paper reviews several problems that arise in the area of design automation and shows most of them to be NP-hard, pointing out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of "interest".
Abstract: This paper reviews several problems that arise in the area of design automation. Most of these problems are shown to be NP-hard. Further, it is unlikely that any of these problems can be solved by fast approximation algorithms that guarantee solutions that are always within some fixed relative error of the optimal solution value. This points out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of "interest".
91 citations
TL;DR: This paper gives concise necessary and sufficient conditions for wirability which are applied to reduce the optimal placement problem to the graph-theoretic single-source-longest-paths problem and concludes that an optimal solution may be determined in linear time.
Abstract: River routing is the problem of connecting a set of terminals a 1,…,a n on a line to another set b 1,…,b n in order across a rectangular channel. When the terminals are located on modules, the modules must be placed relative to one another before routing. This placement problem arises frequently in design systems like bristle-blocks where stretch lines through a module can effectively break it into several chunks, each of which must be placed separately. This paper gives concise necessary and sufficient conditions for wirability which are applied to reduce the optimal placement problem to the graph-theoretic single-source-longest-paths problem. By exploiting the special structure of graphs that arise from the placement problem for rectilinear wiring, an optimal solution may be determined in linear time.
83 citations
01 Jan 1981
TL;DR: Three new two-layer channel routing algorithms are presented that are provably good in that they never require more than 2d-1 horizontal tracks where d is the channel density, when each net connects just two terminals.
Abstract: In this paper we present three new two-layer channel routing algorithms that are provably good in that they never require more than 2d-1 horizontal tracks where d is the channel density, when each net connects just two terminals. To achieve this result, we use a slightly relaxed (but still realistic) wiring model in which wires may run on top of each other for short distances as long as they are on different layers. Two of our algorithms will never use such a “parallel run” of length greater than 2d-1 and our third algorithm will require overlap only at jog points or cross points. Since in this wiring model at least d/2 horizontal tracks are required, these algorithms produce a routing requiring no more than four times the best possible number of horizontal tracks. The second algorithm also has the property that it uses uses at most 4n contacts, where n is the number of nets being connected.
80 citations