scispace - formally typeset
Search or ask a question
Proceedings ArticleDOI

Dominant Structural Factors of Local Residual Stress in Three-Dimensionally Stacked LSI Chips Mounted Using Flip Chip Technology

01 Jan 2007-pp 473-479
TL;DR: In this paper, the authors discuss the stress distribution in chips stacked using area-arrayed metallic bumps and show that the average residual stress in the stacked two chips changes drastically depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending upon the relative position of bumps between an upper and a bottom interconnection layer.
Abstract: Since mechanical stress and strain change both electronic functions and reliability of LSI chips, it has become strongly important to control the residual stress and strain in them to assure their reliable performance. In this study, the authors discuss the stress distribution in chips stacked using area-arrayed metallic bumps. The average residual stress in the stacked two chips changes drastically depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps between an upper and a bottom interconnection layer. However, the residual stress of the top chip with a free surface is not affected by the bump alignment in lower interconnection layers. It is very important, therefore, to optimize the thickness of a chip and other structural factors as mentioned above to control not only the average residual stress but also the amplitude of the periodic stress. Finally, the estimated stress distribution in the stacked two chips was proved in detail by the experiment using stress-sensing chips with 2μm long strain gauges consisted of single-crystalline Si.Copyright © 2007 by ASME
Citations
More filters
Proceedings ArticleDOI
01 Jun 2010
TL;DR: In this article, a set of low-stress test fixtures were developed to eliminate clamping induced stresses being generated during the sensor resistance measurements, and finite element models of the packaging process were developed and correlated with the test chip data.
Abstract: On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.

22 citations


Cites background from "Dominant Structural Factors of Loca..."

  • ...Ueta and Miura [22] have performed some initial measurements of this effect by placing 5 sensors elements between a pair of solder balls at the corner of a flip chip die....

    [...]

Proceedings ArticleDOI
26 Apr 2009
TL;DR: In this article, the authors used test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, CBGA components, and flip chip on laminate assemblies.
Abstract: Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

16 citations


Cites background or methods from "Dominant Structural Factors of Loca..."

  • ...Ueta and Miura [4] have performed some initial measurements die stress gradients by placing 5 sensor elements between a pair of solder balls at the comer of a flip chip die....

    [...]

  • ...Die stress measurements in flip chip assemblies have been performed using test chips [1-7]....

    [...]

Proceedings ArticleDOI
30 Jul 2012
TL;DR: In this article, the authors used on-chip piezoresistive stress sensors to quantify die stress levels induced by microprocessor packaging processes such as flip chip solder joint reflow, underfill cure, and lid attachment.
Abstract: The increasingly complex packaging used in modern workstations and servers transmits a complicated set of mechanical loads to the microprocessor. Increasing die size, high CTE ceramic substrates, lead free solder joints, and ever increasing power requirements have led to increased die stress levels in packaged microprocessor die. Such stresses can degrade silicon device performance, as well as damage the copper/low-k interconnect layers, and in extreme cases, mechanical failure of the die may occur. In previous work of the authors, on-chip piezoresistive stress sensors have been utilized to quantify stress levels induced by microprocessor packaging processes such as flip chip solder joint reflow, underfill cure, and lid attachment. Good correlation has been obtained between the test chip measurements and finite element simulations of the flip chip ceramic ball grid array (FC-CBGA) component assembly process. In the current work, we have extended our past studies on the FC-CBGA microprocessor packaging configuration to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental test chip stress measurements were correlated with finite element simulations of power and thermal cycling events. A sequential modeling approach has been utilized to predict the build-up of die stress. The utilized method incorporates precise thermal histories of the package, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, good correlation has been obtained with the sensor data measured during thermal and power cycling.

15 citations


Cites background from "Dominant Structural Factors of Loca..."

  • ...Ueta and Miura [23] have performed some initial measurements of this effect by placing 5 sensors elements between a pair of solder balls at the corner of a flip chip die....

    [...]

Proceedings ArticleDOI
01 May 2011
TL;DR: In this article, the authors used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of assembly process, as well as due to heat sink clamping and subsequent powered operation.
Abstract: Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the assembly process, as well as due to heat sink clamping and subsequent powered operation. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink was then attached, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A novel sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes and during simulated heat sink clamping.

11 citations


Cites background from "Dominant Structural Factors of Loca..."

  • ...Ueta and Miura [27] have performed some initial measurements of this effect by placing 5 sensors elements between a pair of solder balls at the corner of a flip chip die....

    [...]

Journal ArticleDOI
TL;DR: In this paper, the authors measured the build-up of compressive stresses in a microprocessor die after various steps of the flip chip CBGA assembly process and correlated them with finite element simulations of the clamping process.
Abstract: Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

9 citations