Double-gate tunnel field-effect transistor: Gate threshold voltage modeling and extraction
21 Feb 2014-Journal of Central South University (Central South University)-Vol. 21, Iss: 2, pp 587-592
TL;DR: In this paper, a simple analytical model for DG-TFET gate threshold voltage was built by solving quasi-two-dimensional Poisson equation in Si film, as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric.
Abstract: The tunnel field-effect transistor (TFET) is a potential candidate for the post-CMOS era. As one of the most important electrical parameters of a device, double gate TFET (DG-TFET) gate threshold voltage was studied. First, a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported. Then, a simple analytical model for DG-TFET gate threshold voltage V
TG was built by solving quasi-two-dimensional Poisson equation in Si film. The model as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric was discussed. It is shown that the proposed model is consistent with the simulation results. This model should be useful for further investigation of performance of circuits containing TFETs.
Citations
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TL;DR: In this paper, a new analytical model for the gate threshold voltage of a dual-material double-gate (DMDG) tunnel field effect transistor (TFET) was derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film.
Abstract: A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film and employing the physical definition of $$V_\mathrm{TG}$$VTG. A numerical simulation study of the transfer characteristics and $$V_\mathrm{TG}$$VTG of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of $$V_\mathrm{TG}$$VTG is performed based on the transconductance change method as already used for conventional metal---oxide---semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on $$V_\mathrm{TG}$$VTG are reported. The dependence of $$V_\mathrm{TG}$$VTG on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.
27 citations
TL;DR: In this paper, a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) was used to obtain the superior improvement in terms of different RF and linearity.
Abstract: This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C
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and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.
25 citations
TL;DR: In this paper, a generalized 2D analytical model of gate threshold voltage for multiple material gate tunneling FET (TFET) structures is derived, which includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters.
Abstract: A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.
24 citations
Cites background or methods from "Double-gate tunnel field-effect tra..."
...Besides, comparison with analytical model of [31] for SMDG and [32] for DMDG depicts that the proposed model is a generalized one....
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...Investigations have shown that asymmetric source–drain doping, heterogate dielectric structure, or short gate structures are capable of suppressing the ambipolar device characteristics of TFETs [11]–[13]....
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...At this inflection point, y = wb and ψs f 1(y) = VDS + (kT/q) ln (Ndrain/NCh) [31]....
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...[5] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–745, Aug. 2007....
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...If we consider φm1 = φm2 = φm3 in the derived model of VTH, the model reduces to the threshold voltage model of single material gate TFETs [31]....
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TL;DR: In this paper, the double gate vertical tunnel field effect transistor with homo/hetero dielectric buried oxide (HDB) was used to obtain the optimized device characteristics.
19 citations
TL;DR: This work investigates the impact of work-function engineering for the enhancement of the metrics such as DC, analog/RF and linearity parameters for the low-power, high-speed and high-frequency applications and demonstrates that VTFET offers the superior improvement in terms of steeper subthreshold slope.
18 citations
References
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TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
2,390 citations
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
TL;DR: How the structure of the nanotube is the key enabler of this particular one-dimensional tunneling effect is discussed, which is controlled here by the valence and conduction band edges in a bandpass-filter-like arrangement.
Abstract: A detailed study on the mechanism of band-to-band tunneling in carbon nanotube field-effect transistors (CNFETs) is presented. Through a dual-gated CNFET structure tunneling currents from the valence into the conduction band and vice versa can be enabled or disabled by changing the gate potential. Different from a conventional device where the Fermi distribution ultimately limits the gate voltage range for switching the device on or off, current flow is controlled here by the valence and conduction band edges in a bandpass-filter-like arrangement. We discuss how the structure of the nanotube is the key enabler of this particular one-dimensional tunneling effect.
846 citations
TL;DR: In this paper, the subthreshold swing of field effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET, but instead is shown to be sub-60 mv/dec.
Abstract: A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.
555 citations
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >
466 citations