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Journal ArticleDOI

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs

TL;DR: In this article, a drain current model is developed for a symmetrically driven undoped (or lightly doped) symmetric double-gate MOSFET (SDGFET) under the drift-diffusion transport mechanism, with velocity saturation effects being included as an integral part of the model derivation.
Abstract: A drain current model is developed for a symmetrically driven undoped (or lightly doped) symmetric double-gate MOSFET (SDGFET) under the drift-diffusion transport mechanism, with velocity saturation effects being included as an integral part of the model derivation. Velocity saturation effects are modeled by using the Caughey-Thomas engineering model with exponent n = 2. Id-Vd, Id-Vg, gm -Vg, and gDS-Vd comparisons are made with 2-D device simulation results, and a very good match is found all the way from subthreshold to strong inversion. Gummel symmetry compliance is also shown.

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Citations
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Journal ArticleDOI
TL;DR: In this paper, the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET was studied by using an accurate continuous current?voltage (I?V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation.
Abstract: We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current?voltage (I?V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions (subthreshold, linear and saturation) through a unique continuous expression. Therefore, the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.

29 citations

Journal ArticleDOI
TL;DR: In this paper, an analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel.
Abstract: An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and saturation regions of device operation. The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect. Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated. The model results are validated by numerical simulation results obtained by using the commercially available ATLAS™, a two dimensional device simulator from SILVACO.

17 citations

Journal ArticleDOI
TL;DR: In this paper, a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs is presented, where the drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model.
Abstract: In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

16 citations

Journal ArticleDOI
TL;DR: In this article, surface potential-based analytical models of subthreshold current and sub-reshold swing of the strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs were presented.

12 citations

Journal ArticleDOI
TL;DR: In this paper, a continuous variation of work-function based gate metal has been introduced in conical surrounding gate MOSFETs and a comparative study of the electrostatic and RF characteristics was carried out using TCAD device simulator.

9 citations

References
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Book
Yuan Taur1, Tak H. Ning1
01 Jan 2016
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

2,680 citations


"Drain Current Model Including Veloc..." refers background or result in this paper

  • ...To model CLM in the post-velocity saturation regime, we have used an approach that is similar to that of Ko et al. [25] and Taur and Ning [18] and applied it to a DGFET....

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  • ...and Taur and Ning [18] and applied it to a DGFET....

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  • ...match with experimental data for n-channel devices [18]....

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Journal ArticleDOI
01 Dec 1967
TL;DR: In this article, the experimental dependence of carrier mobilities on doping density and field strength in silicon has been investigated and the curve-fitting procedures are described, which fit the experimental data.
Abstract: Equations are presented which fit the experimental dependence of carrier mobilities on doping density and field strength in silicon. The curve-fitting procedures are described.

1,539 citations


"Drain Current Model Including Veloc..." refers methods in this paper

  • ...References [3] and [13] considered velocity saturation effects by using the Caughey–Thomas model [17] or its variants with exponent n = 1 (the variants (e....

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  • ...We model velocity saturation effects by using the Caughey–Thomas model [17] with exponent n = 2 as...

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  • ...Even though efforts after [17] such as the Canali model [21] have found a good experimental fit using fractional values for...

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Journal ArticleDOI
TL;DR: In this article, the drift velocity of electrons and holes in silicon has been measured in a large range of the electric fields (from 3. 102to 6. 104V/cm) at temperatures up to 430 K. The mean square deviation was in all cases less than 3.8 percent.
Abstract: The drift velocity of electrons and holes in silicon has been measured in a large range of the electric fields (from 3 . 102to 6 . 104V/cm) at temperatures up to 430 K. The experimental data have been fitted with a simple formula for the temperatures of interest. The mean square deviation was in all cases less than 3.8 percent. A more general formula has also been derived which allows to obtain by extrapolation drift velocity data at any temperature and electric field.

591 citations


"Drain Current Model Including Veloc..." refers methods in this paper

  • ...Even though efforts after [17] such as the Canali model [21] have found a good experimental fit using fractional values for...

    [...]

Journal ArticleDOI
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Abstract: Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

413 citations


"Drain Current Model Including Veloc..." refers background in this paper

  • ...DGFETs are more amenable to scaling compared with the conventional MOSFETs by virtue of their better electrostatics [1], [2]....

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Journal ArticleDOI
TL;DR: In this article, a continuous analytic currentvoltage model for double-gate MOSFETs is presented, which is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation.
Abstract: This letter presents a continuous analytic current-voltage (I-V) model for double-gate (DG) MOSFETs. It is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation. The entire I/sub ds/(V/sub g/,V/sub ds/) characteristics for all regions of MOSFET operation: linear, saturation, and subthreshold, are covered under one continuous function, making it ideally suited for compact modeling. By preserving the proper physics, this model readily depicts "volume inversion" in symmetric DG MOSFETs-a distinctively noncharge-sheet phenomenon that cannot be reproduced by standard charge-sheet based I-V models. It is shown that the I-V curves generated by the analytic model are in complete agreement with two-dimensional numerical simulation results for all ranges of gate and drain voltages.

361 citations


"Drain Current Model Including Veloc..." refers background in this paper

  • ...Proceeding as in [5], this can be solved to yield...

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  • ...Using (8) in (7) and proceeding on the same lines as in [5], we finally get (9), shown at the bottom of the page....

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  • ...To the authors’ best knowledge, there has been no work done on modeling velocity saturation effects in DGFETs by using the Caughey–Thomas model with exponent n = 2, where velocity saturation effects are included as an integral part of the model derivation....

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  • ...The limiting case of (9) for the constant mobility case (for vsat = ∞) can be recognized as the exact same equation derived in [5], which had considered mobility to be constant....

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  • ...DGFETs are more amenable to scaling compared with the conventional MOSFETs by virtue of their better electrostatics [1], [2]....

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