Drain Current Optimization in DIBS-Grown MgZnO/CdZnO HFET
TL;DR: In this article, a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnOs (MCO)-based gateless heterostructure field effect transistor (HFET) is presented.
Abstract: This article reports the fabrication of a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnO (MCO)-based gateless heterostructure field-effect transistor (HFET). In addition, this article presents that by introducing a 30-nm yttria spacer layer, the crystallinity of the CdZnO buffer layer can be enhanced and the interface roughness at the heterojunction of the MCO heterostructure can be reduced. Furthermore, the source and drain metal contacts were optimized for the least specific contact resistivity ( $\boldsymbol {\rho }_{c}$ ) yielding metal combination and annealing conditions. The results suggest that the introduction of the yttria spacer layer improves the overall conductance [product of sheet carrier density ( ${n}_{s}$ ) and electron mobility ( $\boldsymbol {\mu }$ )] of MCO up to $3.5\times 10^{15}\,\,\text{V}^{-1}\text{s}^{-1}$ compared to $9\times 10^{14}\,\,\text{V}^{-1}\text{s}^{-1}$ in the non-yttria spacer-based MCO. In addition, the drain current ( ${I}_{d}$ )–drain voltage ( ${V}_{d}$ ) characteristic of the as-developed yttria spacer-based MCO HFET shows a high drain current value (~400 mA/mm). These results establish the DIBS-grown MCO heterostructure as a viable option for low-cost HFETs necessary for the fabrication of large-scale HFET-based power and sensor devices.
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Cites background from "Drain Current Optimization in DIBS-..."
...application displaying strong 2-D electron gas density (2DEG) [13], [14]....
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References
1,365 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...ZnO is being explored as a viable option for heterostructure field-effect transistor (HFET) applications due to the strong polarization fields in the MgZnO/ZnO (MZO) heterostructure [1], [2]....
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876 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...The value of the net resistance (Rt) for different spacing d of metal bars in linear TLM configurations is proportional to the contact resistance (Rc) of the metal and semiconductor interface and sheet resistance (Rs) of the material between the two metal bars in consideration [19]....
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453 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...The least ρc value, for combination I, is generally attributed to the Ni layer preventing Au diffusion through Al and Ti that can degrade the ohmic nature of the metal–semiconductor contact [18]....
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394 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...For polycrystalline materials, higher distance between the two contact pads is plagued by inconsistency and extreme sensitivity to fabrication conditions [20], [21]....
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251 citations
"Drain Current Optimization in DIBS-..." refers background or methods in this paper
...works in [25] and [26], respectively, have gated structures, and the DIBS-grown MCO-II-based HFET fabricated in this article is a gateless structure....
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...5(c) shows the comparison of the Id values achieved in 800 ◦C annealed MCO-II gateless HFET, grown by DIBS, with those obtained from AlGaN/GaN-based [25] and MZObased HFETs [26], both grown by MBE....
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...It should be noted here that the dimensions of D and tb for MBE-grown MZO (D = 3 μm, tb = 2 nm) and AlGaN/GaN-based (D = 5 μm, tb = 40 nm) HFETs are different from the as-developed MCO-II-based HFET (D = 10 μm, tb = 50 nm)....
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...Therefore, in order to carry out a comparative analysis among these three structures, the values of Id for the HFET structures from the works in [25] and [26] are considered at Vg = 0 V....
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