Drain Current Optimization in DIBS-Grown MgZnO/CdZnO HFET
08 May 2020-IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 67, Iss: 6, pp 2276-2281
TL;DR: In this article, a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnOs (MCO)-based gateless heterostructure field effect transistor (HFET) is presented.
Abstract: This article reports the fabrication of a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnO (MCO)-based gateless heterostructure field-effect transistor (HFET). In addition, this article presents that by introducing a 30-nm yttria spacer layer, the crystallinity of the CdZnO buffer layer can be enhanced and the interface roughness at the heterojunction of the MCO heterostructure can be reduced. Furthermore, the source and drain metal contacts were optimized for the least specific contact resistivity ( $\boldsymbol {\rho }_{c}$ ) yielding metal combination and annealing conditions. The results suggest that the introduction of the yttria spacer layer improves the overall conductance [product of sheet carrier density ( ${n}_{s}$ ) and electron mobility ( $\boldsymbol {\mu }$ )] of MCO up to $3.5\times 10^{15}\,\,\text{V}^{-1}\text{s}^{-1}$ compared to $9\times 10^{14}\,\,\text{V}^{-1}\text{s}^{-1}$ in the non-yttria spacer-based MCO. In addition, the drain current ( ${I}_{d}$ )–drain voltage ( ${V}_{d}$ ) characteristic of the as-developed yttria spacer-based MCO HFET shows a high drain current value (~400 mA/mm). These results establish the DIBS-grown MCO heterostructure as a viable option for low-cost HFETs necessary for the fabrication of large-scale HFET-based power and sensor devices.
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TL;DR: In this article, a dual ion beam sputtering (DIBS) system at different deposition conditions in terms of ion beam power, substrate temperature, and time cessation between deposition of successive layers is discussed systematically.
Abstract: Multiple quantum wells (MQWs) of CdZnO/ZnO are realized, for the first time, by dual ion beam sputtering (DIBS) system at different deposition conditions in terms of ion beam power, substrate temperature, and time cessation between deposition of successive layers. The effects of DIBS deposition conditions are analyzed by secondary ion mass spectroscopy (SIMS) and high-resolution transmission electron microscopy (HRTEM) and discussed systematically. The SIMS analysis has been used for depth profiling of CdZnO/ZnO-based MQWs structure. The deposition of CdZnO/ZnO-based MQW structure performed at 100 °C with time cessation of 30 min between successive layer growth and ion beam power of 14 W has displayed the best results in terms of distinct well and barrier layers formation. This work also includes an analytical study of CdZnO/ZnO-based MQW solar cell (MQWSC), in which a study is performed for solar irradiance dependence of performance parameters to explore the potential use of CdZnO/ZnO-based MQWSC for concentrator solar cell (SC). The short-circuit current density increases from 0.12 to 57.98 mA/cm2, the open-circuit voltage rises from 2.60 to 2.77 V, and the photon conversion efficiency is from 2.85% to 3.04%, as solar irradiance increases from 0.1 to 50 suns. The results show that the performance of SCs can be improved by using concentrators and also explore the possibility of efficiently absorbing short-wavelength photons.
10 citations
Cites background from "Drain Current Optimization in DIBS-..."
...application displaying strong 2-D electron gas density (2DEG) [13], [14]....
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TL;DR: In this paper , a stable, highly scalable, reproducible, Y2O3-based memristive crossbar array of (15 × 12) on silicon by utilizing a dual ion beam sputtering system was reported.
Abstract: Transition metal oxides play a very important role to develop the memristive crossbar array for nonvolatile memory for storage and logic operations. However, the development of a high-density memristive crossbar array for complex applications is restricted due to low device yield and high device-to-device (D2D) and cycle-to-cycle (C2C) variability in device switching voltages. Here, we report the fabrication of a stable, highly scalable, reproducible, Y2O3-based memristive crossbar array of (15 × 12) on silicon by utilizing a dual ion beam sputtering system. The fabricated crossbar array exhibits the intrinsic nonlinear characteristics of the memristive element by displaying a high endurance (∼7 × 105 cycles), high current ratio (>200), good retention (∼1.5 × 105 s), high device yield, low device-to-device (D2D) (0.25), and cycle-to-cycle (C2C) (0.608) variability in the SET/RESET voltages of the memristive device, which can be further suitable for analog computation and logic operations.
7 citations
TL;DR: In this article , the electrical performance analysis of a memristive crossbar array (MCA) based on a large Si (100) wafer having a 3-inch diameter by utilizing dual-ion beam sputtering (DIBS) system is reported.
Abstract: Here, we report the electrical performance analysis of a Y2O3-based memristive crossbar array (MCA) of ( $30\,{\times }\,25$ ) on a large Si (100) wafer having a 3-inch diameter by utilizing dual-ion beam sputtering (DIBS) system. The MCA is highly stable and exhibits repeatable and reproducible resistive switching responses in terms of consistent resistive switching voltages ( ${V}_{{\mathrm {SET}}}$ and ${V}_{{\mathrm {RESET}}}$ ). The devices in the MCA efficiently depict the impact of device area scaling on the switching voltage parameters. The fabricated devices also show low device-to-device (D2D) variability in ${V}_{{\mathrm {SET}}}$ (2.64%) ${V}_{{\mathrm {RESET}}}$ (10.13%) and ultralow cycle-to-cycle (C2C) variability in ${V}_{{\mathrm {SET}}}$ (0.2%) and ${V}_{{\mathrm {RESET}}}$ (1.07%). Furthermore, this work also experimentally probes the impacts of various input signal parameters such as applied voltage, compliance current, and pulsewidth (PW) on the variability parameters.
7 citations
TL;DR: In this article , the authors report an implementation of a memristive crossbar array (MCA) out of a total dimension of ( $30\times25$ ) array fabricated by utilizing a dual ion beam sputtering (DIBS) system.
Abstract: Here, we report an implementation of ( $8\times8$ ) $\text{Y}_{{2}}\text{O}_{{3}}$ -based memristive crossbar array (MCA) out of a total dimension of ( $30\times25$ ) array fabricated by utilizing a dual ion beam sputtering (DIBS) system. The selected ( $8\times8$ ) MCA is further used to electrically write random alphabets and perform synaptic learning characteristics to perform analog and neuromorphic computing applications. The MCA effectively exhibits multiple current levels and mimics various artificial synaptic properties with superior bidirectional switching responses. The MCA mimics potentiation, depression, and different Hebbian learning-based spike-time-dependent plasticity rules, suggesting the importance of the $\text{Y}_{{2}}\text{O}_{{3}}$ -based MCA for large-scale neuromorphic and analog computations. This work provides different insights into the design of an artificial synapse by utilizing $\text{Y}_{{2}}\text{O}_{{3}}$ as a switching oxide in memristors.
3 citations
05 Jan 2022
TL;DR: The fabrication of an Y2O3-based memristive crossbar array along with an analytical model to evaluate the performance of the Memristive array system and the obtained results confirm that the effect of variation in electrical stimuli on forgetting and retention is similar to the biological brain.
Abstract: Here, we report the fabrication of an Y2O3-based memristive crossbar array along with an analytical model to evaluate the performance of the memristive array system to understand the forgetting and retention behavior in the neuromorphic computation. The developed analytical model is able to simulate the highly dense memristive crossbar array-based neural network of biological synapses. These biological synapses control the communication efficiency between neurons and can implement the learning capability of the neurons. During electrical stimulation of the memristive devices, the memory transition is exhibited along with the number of applied voltage pulses, which is analogous to the real human brain functionality. Further, to obtain the forgetting and retention behavior of the memristive devices, a modified window function equation is proposed by incorporating two novel internal state variables in the form of forgetting rate and retention. The obtained results confirm that the effect of variation in electrical stimuli on forgetting and retention is similar to that of the biological brain. Therefore, the developed analytical memristive model can further be utilized in the memristive system to develop real-world applications in neuromorphic domains.
2 citations
References
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TL;DR: In this paper, a combination of high resolution x-ray diffraction, atomic force microscopy, Hall effect, and capacitance-voltage profiling measurements is used to calculate the polarization induced sheet charge bound at the AlGaN/GaN interfaces.
Abstract: Two dimensional electron gases in Al x Ga 12x N/GaN based heterostructures, suitable for high electron mobility transistors, are induced by strong polarization effects. The sheet carrier concentration and the confinement of the two dimensional electron gases located close to the AlGaN/GaN interface are sensitive to a large number of different physical properties such as polarity, alloy composition, strain, thickness, and doping of the AlGaN barrier. We have investigated these physical properties for undoped and silicon doped transistor structures by a combination of high resolution x-ray diffraction, atomic force microscopy, Hall effect, and capacitance‐voltage profiling measurements. The polarization induced sheet charge bound at the AlGaN/GaN interfaces was calculated from different sets of piezoelectric constants available in the literature. The sheet carrier concentration induced by polarization charges was determined
1,439 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...ZnO is being explored as a viable option for heterostructure field-effect transistor (HFET) applications due to the strong polarization fields in the MgZnO/ZnO (MZO) heterostructure [1], [2]....
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TL;DR: In this article, it was shown that the contact end resistance and the consequent specific contact resistance can be deduced from simple resistance measurements carried out between contacts on a standard, transmission line model test pattern.
Abstract: In characterizing ohmic contacts using the transmission line model, it is necessary to make a measurement referred to as the contact end resistance, as a result of modification to the sheet resistance under the contact. In this article we show that this contact end resistance and the consequent specific contact resistance can be deduced from simple resistance measurements carried out between contacts on a standard, transmission line model test pattern.
947 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...The value of the net resistance (Rt) for different spacing d of metal bars in linear TLM configurations is proportional to the contact resistance (Rc) of the metal and semiconductor interface and sheet resistance (Rs) of the material between the two metal bars in consideration [19]....
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TL;DR: In this article, a new metallization process for achieving low resistance ohmic contacts to molecular beam epitaxy grown n−GaN (∼1017 cm−3) using an Al/Ti bilayer metallisation scheme was reported.
Abstract: We report a new metallization process for achieving low resistance ohmic contacts to molecular beam epitaxy grown n‐GaN (∼1017 cm−3) using an Al/Ti bilayer metallization scheme. Four different thin‐film contact metallizations were compared during the investigation, including Au, Al, Ti/Au, and Ti/Al layers. The metals were first deposited via conventional electron‐beam evaporation onto the GaN substrate, and then thermally annealed in a temperature range from 500 to 900 °C in a N2 ambient using rapid thermal annealing techniques. The lowest value for the specific contact resistivity of 8×10−6 Ω cm2, was obtained using Ti/Al metallization with anneals of 900 °C for 30 s. X‐ray diffraction and Auger electron spectroscopy depth profile were employed to investigate the metallurgy of contact formation.
464 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...The least ρc value, for combination I, is generally attributed to the Ni layer preventing Au diffusion through Al and Ti that can degrade the ohmic nature of the metal–semiconductor contact [18]....
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TL;DR: In this paper, various methods for organic semiconductor deposition are reviewed, and recent progress in printing and patterning of OTFTs are surveyed, as well as their application in future plastic electronic devices.
Abstract: Organic thin film transistors (OTFTs) will play an important role in future plastic electronic devices. The device performance is greatly affected by the molecular structure and morphology of the organic semiconductors. Various methods for organic semiconductor deposition are reviewed. Recent progress in printing and patterning of OTFTs are also surveyed.
407 citations
"Drain Current Optimization in DIBS-..." refers background in this paper
...For polycrystalline materials, higher distance between the two contact pads is plagued by inconsistency and extreme sensitivity to fabrication conditions [20], [21]....
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TL;DR: In this article, the performance results of AlGaN-GaN Heterostructure Field Effect Transistors (HFETs) grown on SiC substrates are reported, and the maximum transconductance of these devices was 142 mS/mm and the source-drain current was as high as 0.95 A/mm.
Abstract: The performance results AlGaN-GaN Heterostructure Field Effect Transistors (HFETs) grown on SiC substrates are reported. The maximum transconductance of these devices was 142 mS/mm and the source-drain current was as high as 0.95 A/mm. The maximum dissipated DC power at room temperature was 0.6 MW/cm/sup 2/, which is more than three times higher than that in similar devices grown on sapphire. This high thermal breakdown threshold was achieved primarily due to the effective heat sink through the SiC substrate. These devices demonstrated stable performance at elevated temperatures up to 250/spl deg/C. The source-drain current saturation was observed up to 300/spl deg/C. The leakage current in the below threshold regime was temperature-activated with an activation energy of 0.38 eV.
259 citations
"Drain Current Optimization in DIBS-..." refers background or methods in this paper
...works in [25] and [26], respectively, have gated structures, and the DIBS-grown MCO-II-based HFET fabricated in this article is a gateless structure....
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...5(c) shows the comparison of the Id values achieved in 800 ◦C annealed MCO-II gateless HFET, grown by DIBS, with those obtained from AlGaN/GaN-based [25] and MZObased HFETs [26], both grown by MBE....
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...It should be noted here that the dimensions of D and tb for MBE-grown MZO (D = 3 μm, tb = 2 nm) and AlGaN/GaN-based (D = 5 μm, tb = 40 nm) HFETs are different from the as-developed MCO-II-based HFET (D = 10 μm, tb = 50 nm)....
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...Therefore, in order to carry out a comparative analysis among these three structures, the values of Id for the HFET structures from the works in [25] and [26] are considered at Vg = 0 V....
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