Journal ArticleDOI
DRAMSim2: A Cycle Accurate Memory System Simulator
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TLDR
The process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results is described.Abstract:
In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results. We outline the combination of DRAMSim2 with a cycle-accurate x86 simulator that can be used to perform full system simulations. Finally, we discuss DRAMVis, a visualization tool that can be used to graph and compare the results of DRAMSim2 simulations.read more
Citations
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Journal ArticleDOI
Ramulator: A Fast and Extensible DRAM Simulator
TL;DR: This paper presents Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility, and is able to provide out-of-the-box support for a wide array of DRAM standards.
Journal ArticleDOI
RAIDR: Retention-Aware Intelligent DRAM Refresh
TL;DR: This paper proposes RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times and group DRAM rows into retention time bins and apply a different refresh rate to each bin.
Proceedings ArticleDOI
ZSim: fast and accurate microarchitectural simulation of thousand-core systems
TL;DR: Zsim, a fast, scalable, and accurate simulator, is built using bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy, and lightweight user-level virtualization is implemented to support complex workloads.
Journal ArticleDOI
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
TL;DR: NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies is developed.
Journal ArticleDOI
A case for exploiting subarray-level parallelism (SALP) in DRAM
TL;DR: Three new mechanisms (SALP-1, SALP-2, and MASA) mitigate the negative impact of bank serialization by overlapping different components of the bank access latencies of multiple requests that go to different subarrays within the same bank.
References
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Proceedings ArticleDOI
The PARSEC benchmark suite: characterization and architectural implications
TL;DR: This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.
Book
Memory Systems: Cache, DRAM, Disk
TL;DR: Is your memory hierarchy stopping your microprocessor from performing at the high level it should be?
Proceedings ArticleDOI
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
TL;DR: Why PTLsim's x86 focus is highly relevant, and the full system simulation results are used to demonstrate the pitfalls of userspace only simulation, are described.
Journal ArticleDOI
DRAMsim: a memory system simulator
TL;DR: DRAMsim is introduced, a detailed and highly-configurable C-based memory system simulator that implements detailed timing models for a variety of existing memories, including SDRAM, DDR, DDR2, DRDRAM and FB-DIMM, with the capability to easily vary their parameters.
Journal ArticleDOI
The structural simulation toolkit
Arun Rodrigues,Karl Scott Hemmert,Brian W. Barrett,C. Kersey,Ron A. Oldfield,M. Weston,R. Risen,Jeanine Cook,Paul Rosenfeld,Elliott Cooper-Balis,Bruce Jacob +10 more
TL;DR: The Structural Simulation Toolkit (SST) as discussed by the authors is an open, modular, parallel, multi-criteria, multiscale simulation framework for HPC systems that includes a number of processor, memory, and network models.