Dynamic reconfigurable computing architecture for aerospace applications
07 Mar 2009-pp 1-6
TL;DR: The design and prototyping of a computing architecture which dynamically reconfigures itself depending on the environment in which it resides is presented, ideal for robust, real-time applications such as spacecraft control systems.
Abstract: This paper presents the design and prototyping of a computing architecture which dynamically reconfigures itself depending on the environment in which it resides. The system switches among three modes of operation (parallel processing, low power, and radiation tolerant) depending on an external radiation sensor and application input from the user. The system was prototyped on a Xilinx Virtex-5 FPGA to verify its feasibility when controlling a series of peripherals under the three modes of operation. This type of system is ideal for robust, real-time applications such as spacecraft control systems.
Citations
More filters
25 Aug 2014
TL;DR: Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor, enabling ECU consolidation and bandwidth reduction.
Abstract: Cyber Physical Systems (CPSs), such as those found in modern vehicles, include a number of important time and safety-critical functions. Traditionally, applications are mapped to several dedicated electronic control units (ECUs), and hence, as new functions are added, compute weight and cost increase considerably.%ECU consolidation, where multiple functions are combined on fewer ECUs is an important area, but traditional software ECUs fail to offer the required performance, parallelism, and isolation to support this. With increasing computational and communication demands, traditional software ECUs fail to offer the required performance to provide determinism and predictability, while multi-core approaches fail to provide sufficient isolation between tasks. Hybrid FPGAs, combining a processor and reconfigurable fabric on a single die, allow for parallel hardware implementation of complex sensor processing tightly coupled with the flexibility of software on a processor. We demonstrate the advantages of such architectures in consolidating distributed processing with predictability, determinism and isolation, enabling ECU consolidation and bandwidth reduction.
16 citations
Cites background from "Dynamic reconfigurable computing ar..."
...Although they have yet to achieve mass-adoption in the automotive industry, they have been widely used in vision-based automotive systems, and use in more fundamental functions has been proposed in the literature....
[...]
Dissertation•
01 Jan 2013
TL;DR: In this paper, the Xilinx Virtex-5QV is the first commercially available Radiation Hardened By Design (RHBD) SRAM-based FPGA; however, not all of its internal components are hardened against radiation-induced errors.
Abstract: SRAM-based FPGAs are highly attractive for space
applications due to their in-flight reconfigurability, decreased
development time and cost, and increased design and testing
flexibility. The Xilinx Virtex-5QV is the first commercially
available Radiation Hardened By Design (RHBD) SRAM-based FPGA;
however, not all of its internal components are hardened against
radiation-induced errors. This thesis examines and quantifies the
additional considerations and techniques designers should employ
with a RHBD SRAM-based FPGA in a space-based processing system to
achieve high operational reliability. Additionally, this work
presents the application of some of these techniques to the
embedded avionics design of the REXIS imaging payload on the
OSIRIS-REx asteroid sample return mission.
13 citations
Cites background from "Dynamic reconfigurable computing ar..."
...Given the the power consumption increase is small for each added MicroBlaze, designing a system with multiple MicroBlazes could prove an attractive option for robustness and redundancy against radiation-induced errors [60]....
[...]
Dissertation•
28 Apr 2011
TL;DR: It was possible to show that the proposed fault tolerant scheme based on information redundancy leads to a better implementation and provides better SEU resistance than the traditional Triple Modular Redundancy (TMR).
Abstract: Spacecrafts are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, there has been an increasing demand to utilize strong cryptographic primitives to assure their security. Moreover, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. The problem of recovering spacecrafts from failures or attacks, and bringing them back to an operational and safe state is crucial for reliability. Despite the recent interest in incorporating on-board security, there is limited research in this area. This research proposes a trusted hardware module approach for recovering the spacecrafts subsystems and their cryptographic capabilities after an attack or a major failure has happened. The proposed fault tolerant trusted modules are capable of performing platform restoration as well as recovering the cryptographic capabilities of the spacecraft. This research also proposes efficient fault tolerant architectures for the secure hash (SHA-2) and message authentication code (HMAC) algorithms. The proposed architectures are the first in the literature to detect and correct errors by using Hamming codes to protect the main registers. Furthermore, a quantitative analysis of the probability of failure of the proposed fault tolerance mechanisms is introduced. Based upon an extensive set of experimental results along with probability of failure analysis, it was possible to show that the proposed fault tolerant scheme based on information redundancy leads to a better implementation and provides better SEU resistance than the traditional Triple Modular Redundancy (TMR). The fault tolerant cryptographic primitives introduced in this research are of crucial importance for the implementation of on-board security in spacecrafts.
7 citations
Cites background or methods from "Dynamic reconfigurable computing ar..."
...17 PicoBlaze Platform in (a) Fault Tolerant and (b) Parallel Processing Modes from [99] ....
[...]
...17: PicoBlaze Platform in (a) Fault Tolerant and (b) Parallel Processing Modes from [99]...
[...]
...An adaptive platform is presented in [99], which dynamically reconfigure itself to match the environment currently faced by the computational platform....
[...]
11 May 2016
7 citations
Additional excerpts
...This provides a promising approach for FPGAs, which have been widely employed in several time-critical applications in aerospace [174, 175], telecommunications [176], and the medical domain [177]....
[...]
TL;DR: This article reviews existing methodologies and technologies for RCAs with a strong emphasis on computing granularity and agile management of resources and concludes that there are just few certifable RCA devices for aerospace.
Abstract: Computing and processing capabilities from reconfgurable computer architectures (RCAs) can provide high-integrity avionics systems with outstanding effciency and effectiveness, as they do in other domains. However, they are still underexploited in many applications. The main driver of this situation is that devices implementing such architectures are too advanced and powerful for the system's needs. The situation in avionics is even worst, because there are just few certifable RCA devices for aerospace. In addition, the fexible nature of RCAs incurs high costs and risks along the system development life cycle (certifcation processes).
7 citations
Cites background from "Dynamic reconfigurable computing ar..."
...Field programmable processor array [16] Virtex-5 [18] (FPGA)...
[...]
References
More filters
01 Jan 1986-International Journal of Radiation Applications and Instrumentation. Part C. Radiation Physics and Chemistry
TL;DR: A review of the physical mechanisms by which radiation dose is registered by RADFETs, describes the characteristics and performance of a practical RadFET, and discusses applications as discussed by the authors.
203 citations
"Dynamic reconfigurable computing ar..." refers methods in this paper
...A number of sensing techniques have been demonstrated that can be used to monitor for radiation in VLSI systems including RADFETs [10], Total Ionizing Dose (TID) monitors [11], and built-in current sensors (BICS) [12,13]....
[...]
14 Jul 2004
TL;DR: In this article, 3D packaging poses two challenges: 1) the stacking of more chips in a thinner package stretches the performance envelope of all assembly process, materials and equipment, and 2) the testing of the final module requires that package design allow access to all the chips.
Abstract: Cell phones and consumer products like digital cameras, PDAs and other wireless devices require maximum functional integration in the smallest footprint, lowest profile and low cost package. CSPs have minimized the footprint to achieve a chip/package area ratio about 80%. 3D packaging has increased that ratio to the impressive level of > 200% without increasing the thickness or the footprint of the package. Integration in the z-direction is achieved by stacking die or stacking packages and interconnecting them with wire bonding. 3D packages are assembled using the established packaging infrastructure and supply chain which offers design flexibility, short time-to-market, low risk and low cost product introduction. 3D packaging poses two challenges. First, the stacking of more chips in a thinner package stretches the performance envelope of all assembly process, materials and equipment. Narrower process margins, thin layer materials, equipment with higher precision and flexibility require trade-offs to minimize risk and cost without compromising the reliability of the package. Second, the testing of the final module requires that package design allow access to all the chips. Integration of complex chips from multiple suppliers in one package creates a high value module and increased test complexity.
86 citations
"Dynamic reconfigurable computing ar..." refers background in this paper
...System-inPackage (SiP) technology has enabled the integration of low cost radiation sensors within the same package as traditional CMOS substrates to notify the computing system when radiation is present [8,9]....
[...]
07 Mar 2005
TL;DR: A new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM is proposed and found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.
Abstract: We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.
82 citations
"Dynamic reconfigurable computing ar..." refers methods in this paper
...A number of sensing techniques have been demonstrated that can be used to monitor for radiation in VLSI systems including RADFETs [10], Total Ionizing Dose (TID) monitors [11], and built-in current sensors (BICS) [ 12 ,13]....
[...]
04 Mar 2006
TL;DR: A framework that allows Earth and space scientists to use FPGA resources through an abstraction layer is explored, and a synthetic aperture radar application is used to demonstrate the power of the system architecture.
Abstract: Complex real-time signal and image processing applications require low-latency and high-performance hardware to achieve optimal performance. Building such a high-performance platform for space deployment is hampered by hostile environmental conditions and power constraints. Custom space-based FPGA coprocessors help alleviate these constraints, but their use is typically restricted by the need for TMR or radiation-hardened components. This paper explores a framework that allows Earth and space scientists to use FPGA resources through an abstraction layer. A synthetic aperture radar application is used to demonstrate the power of the system architecture. The performance of the application is shown to achieve a speedup of 19 when compared to a software solution and is able to maintain comparable data reliability. Projected speedups, for the same case study executing on the proposed flight system architecture, are several times better and also discussed. This work supports the Dependable Multiprocessor project at Honeywell and the University of Florida, a mission for the Space Technology 8 (ST-8) satellite of NASA's New Millennium Program.
42 citations
"Dynamic reconfigurable computing ar..." refers background in this paper
...With the recent advances in the size and performance of Field Programmable Gate Arrays (FPGA), there is now a cost efficient path to implementing multiple processors in a single part while still meeting performance specifications [4,5]....
[...]
21 Oct 1995
TL;DR: This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction in CMOS static RAMs.
Abstract: This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.
41 citations
"Dynamic reconfigurable computing ar..." refers methods in this paper
...A number of sensing techniques have been demonstrated that can be used to monitor for radiation in VLSI systems including RADFETs [10], Total Ionizing Dose (TID) monitors [11], and built-in current sensors (BICS) [12,13]....
[...]