Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon
Summary (3 min read)
1. INTRODUCTION
- With the dramatic downscaling of layout geometries, the traditional bulk CMOS technology has hit critical roadblocks, namely increasing leakage current and power consumption induced by the short-channel effects (SCEs) and the increasing variability levels.
- This is an important point because the delay versus temperature behavior of FinFET devices and circuits is different from that of the conventional bulk CMOS devices operating in the super-threshold regime.
- In the near/subthreshold regime [12, 13] or in high-vt devices [14], it has been reported that the delay of these circuits decreases with increasing temperature.
- The authors effectively find the optimal temperature point to maximize energy efficiency of the circuits, and introduce new voltage scaling policies to make the circuits operate at the optimal point.
2. TEMPERATURE EFFECT INVERSION (TEI) PHENOMENON IN FinFETs
- For VLSI circuits, the delay of a logic gate is directly affected by the driving current (Ion).
- S, µ, and Vth are the temperature dependent parameters.
- Meanwhile, conventional MOSFETs operating in the sub/nearthreshold regime or high-vt devices have shown the similar phenomenon (indeed, more significant than what was observed in FinFETs with super-threshold Vdd) that the circuit delay decreases with the increasing temperature [12, 13, 14].
- As a consequence, different from the super-threshold regime where the slightly stronger effect of µ than that of Vth causes decreasing Ion with increasing T , the changes of Vth and S considerably increases Ion in the sub/near-threshold regime, and thus the gate can run much faster.
- Ion of FinFETs operating in the sub/near-threshold regime also has the same exponential dependency on Vth and S. Combined with the tensile stress effect, FinFETs in the sub/near-threshold regime exhibit a significant delay reduction as the temperature goes high.
3. POWER AND THERMAL MODELS
- The power consumption of VLSI circuits has two components: a dynamic part and static part.
- The authors use the conventional RC-circuit thermal model, which is shown in Figure 4 (a) [19].
- Due to the strong dependence of Pstatic on Tdie and Vdd from (2), the amount of differences between the two Pcircuit levels from the high Vdd and low Vdd , which is indicated by the arrows in Figure 4 (b), increases super-linearly with increasing Tdie and Vdd .
- Hence, for some high Vdd levels, it is possible that the corresponding Teq’s exceed the die temperature limit (e.g., 90°C), or such Teq’s do not exist at all.
- The details will be explained at Section 5.
4.1 Influence of TEI on energy consumption
- Due to the TEI phenomenon, the worst-case delays occur at the low temperature in FinFET circuits.
- Therefore, for a given target clock frequency, the corresponding voltage level of the circuit should be set according to the worst-cased circuit delay, which occurs at the lowest die temperatures.
- Lowering down the voltage levels right after the increased temperature reaching Tth leads to two possible cases: (Case I) Tdie keeps increasing, or (Case II) Tdie begins decreasing.
- Different from Figure 5 (b) and (c), each of which considers simply two available voltage levels, there can be more than two available voltages levels in reality that can meet the scheduled frequency condition in the whole temperature range.
4.2 Energy optimization
- With the given deadline specification of a task, the required (min- imum) operating frequency ftarget and corresponding base voltage level Vbase can be determined in order to finish task execution by deadline.
- Conventional DTMs of the circuit try not to exceed the temperature limit Tlimit by forcing to lower down the frequency or stop execution with performance penalties.
- Therefore, the authors propose a policy as: I Policy I: Check if there exists a k such that TVkeq ∈.
- If k exists, the optimal voltage level is Vk and the optimal and stable temperature is TVkeq .
- Tdie keeps increasing in all the regions until the region i with TVieq lower than TVith .
5. EXPERIMENTAL WORK
- The authors validated their proposed DTM with various FinFET-based circuits, namely, 50 FO4 inverter chain, 16-bit carry-select adder, 16- bit multiplier, and 16-bit comparator based on 10nm, 14nm, 16nm, and 20nm PTM-MG bulk FinFET libraries.
- The delays were obtained from the worst case inputs of the circuits.
- The authors found the scaling factor s, such that multiplying s to the power data from the 20nm based inverter chain makes the temperature increase of the circuit (working with 0.7V) follow the same trend of ARM Cortex-A8.
- The authors defined Gain = Saved energy w/ the proposed DTM·100(%)Energy consumption w/ the conventional DTM .
- The authors also determined the simulation conditions as follows: (i) the base Vdd in the simulation is assumed to be the minimum voltage level, that the circuit controlled by the conventional DTM can finish a given task with the base Vdd before the temperature exceeds 90°C or its Teq, and (ii) the circuit starts the operation at the ambient temperature (25°C).
6. CONCLUSION
- This paper started by presenting a key observation of TEI phenomenon that the delay of a FinFET gate decreases with increasing die temperature both in the near and super-threshold voltage regimes, which is different from that exhibited by planar CMOS devices operating at the super-threshold Vdd .
- Next it introduced the TEI-aware DTM algorithm to minimize the energy consumption of FinFET-based circuits without any appreciable performance penalty.
- More precisely, instead of choosing the smallest possi- ble voltage to complete a task within its specified deadline, the proposed DTM algorithm dynamically adjusts the supply voltage of the chip so as to maintain the chip temperature at or near its optimum operation point.
- Experimental results showed 40% energy saving (with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.
Did you find this useful? Give us your feedback
Citations
63 citations
28 citations
Cites background from "Dynamic thermal management for FinF..."
...TEI and different threshold voltages are responsible for the transistor current differences in response to increased temperature....
[...]
...This inverted temperature dependence (ITD) is called temperature effect inversion (TEI) [11]....
[...]
26 citations
Cites background or result from "Dynamic thermal management for FinF..."
...Existing work has already exploited this behavior for energy [18] and performance [2] optimization purposes, using the key insight that the TEI-induced tensile stress causes a slight increase in the carrier mobility....
[...]
...This more complicated coupling effect with counteracting interdependencies has been previously studied and motivated by different groups [18, 2, 22]....
[...]
...[18] proposed a dynamic thermal management policy for FinFET-based circuits that exploits the TEI...
[...]
...These observations are consistent with the results and the terminology used by several research groups: temperature effect inversion [18, 2], temperature- and time-critical [8], voltage- and time- acceleration [16]....
[...]
...iso-power or iso-frequency operation [2, 18]....
[...]
24 citations
23 citations
References
882 citations
"Dynamic thermal management for FinF..." refers background in this paper
...This is due to more effective channel Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page....
[...]
...This is due to more effective channel Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full…...
[...]
767 citations
695 citations
"Dynamic thermal management for FinF..." refers background in this paper
...…the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET-based circuits without any appreciable performance penalty....
[...]
443 citations
413 citations
Related Papers (5)
Frequently Asked Questions (22)
Q2. What is the effect of using lower voltage levels on the circuit?
using lower voltage levels slows down the temperature rise so that the circuit can operate with at a high frequency for longer time, while the circuit controlled by conventional DTMs would have to reduce the frequency earlier than the proposed DTM.
Q3. Why is the circuit getting faster with rising temperature?
Because of the TEI phenomenon, the FinFET-based circuit is getting faster with rising temperature, which allows us to drop the supply voltage level below Vbase while maintaining ftarget .
Q4. What are the common DTM mechanisms?
Several DTM response mechanisms (control knobs) e.g., fetch-toggling, dynamic thread migration, frequency throttling and DVFS, have been introduced [7, 8, 9].
Q5. What is the purpose of the proposed DTM?
Their proposed DTM method targets to minimize the energy consumption for a given task, or a given set of tasks, without violating the operating frequency of the initial schedule, and thereby without any performance loss.
Q6. What is the way to reduce the energy consumption of a conventional MOSFET?
For a conventional MOSFET operating at superthreshold Vdd (e.g., 0.9 V), it is well known that the rising temperature will result in a reduced Ion and eventually aggravate the speed of circuit.
Q7. What is the effect of the tensile stress on the FET?
Double-gate FinFET device structure.ture, the tensile stress becomes larger, which decreases Vth as well as induces a slight change of the carrier mobility µ for FinFETs.
Q8. What are the drawbacks of the bulk CMOS technology?
With the dramatic downscaling of layout geometries, the traditional bulk CMOS technology has hit critical roadblocks, namely increasing leakage current and power consumption induced by the short-channel effects (SCEs) and the increasing variability levels.
Q9. How can the proposed DTM approach reduce energy consumption without performance penalty?
Experimental results demonstrate some 40% energy saving (with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.
Q10. What is the main reason for the increase in power density of bulk CMOS?
as power density has continued to increase with the technology scaling, the accompanying high rate of heat generation has become a growing concern.
Q11. What is the effect of a DTM on the circuit?
their DTM slows down the speed of temperature increase, or makes the die temperature stable at a certain point below Tlimit , thereby avoiding the performance loss from such situations when the conventional DTMs inevitably lower the frequency or stop execution.
Q12. What is the motivation for scaling down the delay?
Given a DVFS schedule derived from the worst-case (at, say, -25°C) delay at various voltage levels, the motivation is to scale down the voltage level when the circuit temperature is high enough such that the delay from the lower volt-age level is no larger than the worst-case delay from the original higher voltage level.
Q13. What is the effect of the leakage current on the circuit?
The leakage current of a circuit increases exponentially with the increasing temperature [6] and this positive feedback mechanism between leakage power and temperature can result in a thermal runaway situation.
Q14. Why do the authors not include a separate heatsink?
Notice that, if the authors target a large scale chip that equips heatsinks or coolers, the spatial thermal variations should be taken into consideration, which may require to develop the more sophisticated thermal models and accompanying control logics (e.g., the feedback controller) to be robust to the modeling errors.
Q15. How can the authors determine the minimum operating frequency of a task?
With the given deadline specification of a task, the required (min-imum) operating frequency ftarget and corresponding base voltage level Vbase can be determined in order to finish task execution by deadline.
Q16. What is the description of the DTM work?
The previous DTM works have tackled the question of how to limit the peak temperature on circuit substrates comprised of planar CMOS devices running in the super-threshold voltage regime to save power or maximize performance.
Q17. How did the authors determine the equilibrium temperature for each circuit?
Based on the scaled power and the ambient temperature set to 25°C, the authors finally derived the equilibrium temperature for each circuit and each voltage level.
Q18. What is the way to set the voltage level of a circuit?
for a given target clock frequency, the corresponding voltage level of the circuit should be set according to the worst-cased circuit delay, which occurs at the lowest die temperatures.
Q19. What is the main reason why the proposed DTM can achieve significant energy reduction without performance penalty?
This method can achieve significant energy reduction without performance penalty due to the following three reasons: (i) lowering down the voltage level will quadratically reduce the dynamic energy of the circuit and also reduce the leakage energy/power, (ii) lowering down the voltage level may slow down the rising speed of temperature, or may even reduce the temperature in presence of a heatsink (e.g., the ambient environment for mobile devices), and will exponentially reduce the leakage power, and (iii) the operating frequency determined by the worst-case delay of the higher original voltage can be maintained after the voltage scaling.
Q20. What is the minimum constraint of a voltage controller?
The minimum constraint of such warm-up time is determined by the voltage switching time (i.e., the voltage transition latency of DC-DC converters) that the voltage controller can provide.
Q21. What is the effect of Vth on Ion in the sub-threshold regime?
As a consequence, different from the super-threshold regime where the slightly stronger effect of µ than that of Vth causes decreasing Ion with increasing T , the changes of Vth and S considerably increases Ion in the sub/near-threshold regime, and thus the gate can run much faster.
Q22. Where is the minimum energy point in each region located?
As can be seen from the figure, the minimum energy point in each region locates at the temperature point where the voltage level is changed, i.e., the threshold temperature level.