EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA
03 May 2020-pp 242-242
TL;DR: Although SNN has been blamed for the relatively lower accuracy, recent studies on converted SNNs have improved its accuracy to a similar level of ANN and CNN for smaller network models like MNIST and CIFAR-10, and have demonstrated the great potential of SNN in future deep learning systems.
Abstract: Neural networks (NNs) have been widely used in many machine learning algorithms and have been deployed for various industrial applications like image classification, speech recognition, and automated control. Spiking neural network (SNN), known as the third-generation neural network, incorporates timing information in the network and is more biologically plausible [1]. Compared to today's artificial and convolutional neural networks (ANN and CNN) where all neurons in each layer will always be activated and computed, SNN only activates those neurons whose membrane potential exceed the threshold potential [2]. As a result, SNN requires fewer computation resources and less data communication between network layers due to its event-driven nature. Although SNN has been blamed for the relatively lower accuracy, recent studies on converted SNNs have improved its accuracy to a similar level of ANN and CNN for smaller network models like MNIST and CIFAR-10, and have demonstrated the great potential of SNN in future deep learning systems [2].
Citations
More filters
01 Dec 2022
TL;DR: In this paper , an event-driven spiking convolution architecture with multi-kernel and multi-layer capability is designed, which can be configured in multiple-spike (MS) mode or single spike (SS) mode to adapt to different SCNN models with either rate coding scheme or temporal coding scheme.
Abstract: In this brief, an event-driven spiking convolution architecture with multi-kernel and multi-layer capability is designed. The proposed architecture can be configured in multiple-spike (MS) mode or single-spike (SS) mode to adapt to different spiking convolution neural network (SCNN) models with either rate coding scheme or temporal coding scheme. A skipped zero kernel step is designed to reduce access neuron membrane potentials in memories. In addition, the proposed design supports two pooling methods for increasing flexibility. The proposed architecture is implemented in a Xilinx Kintex-7 FPGA development board, and two SCNN models with different coding schemes are applied to verify the efficiency of the architecture. For the first SCNN model with rate coding scheme, the proposed architecture achieves a 99% classification accuracy with 0.46 mJ/classification. For the second SCNN model with temporal coding scheme, the proposed architecture obtains a classification accuracy over 95.4% with 7.4 uJ/classification. Experimental results demonstrate that the proposed design is adaptable and has a low power consumption overhead.
2 citations
TL;DR: The proposed solution has been implemented on the Xilinx Zynq 7020 All-Programmable SoC and can emulate fully connected spiking neural networks counting up to 3,098 Izhikevich neurons and 9.6e6 synapses in real-time, with a resolution of 0.1 ms.
Abstract: Closed-loop experiments involving biological and artificial neural networks would improve the understanding of neural cells functioning principles and lead to the development of new generation neuroprosthesis. Several technological challenges require to be faced, as the development of real-time spiking neural network emulators which could bear the increasing amount of data provided by new generation High-Density Multielectrode Arrays. This work focuses on the development of a real-time spiking neural network emulator addressing fully-connected neural networks. This work presents a new way to increase the number of synapses supported by real-time neural network accelerators. The proposed solution has been implemented on the Xilinx Zynq 7020 All-Programmable SoC and can emulate fully connected spiking neural networks counting up to 3,098 Izhikevich neurons and 9.6e6 synapses in real-time, with a resolution of 0.1 ms.
2 citations
TL;DR: In this paper , an event-driven spiking convolution architecture with multi-kernel and multi-layer capability is designed, which can be configured in multiple-spike (MS) mode or single spike (SS) mode to adapt to different SCNN models with either rate coding scheme or temporal coding scheme.
Abstract: In this brief, an event-driven spiking convolution architecture with multi-kernel and multi-layer capability is designed. The proposed architecture can be configured in multiple-spike (MS) mode or single-spike (SS) mode to adapt to different spiking convolution neural network (SCNN) models with either rate coding scheme or temporal coding scheme. A skipped zero kernel step is designed to reduce access neuron membrane potentials in memories. In addition, the proposed design supports two pooling methods for increasing flexibility. The proposed architecture is implemented in a Xilinx Kintex-7 FPGA development board, and two SCNN models with different coding schemes are applied to verify the efficiency of the architecture. For the first SCNN model with rate coding scheme, the proposed architecture achieves a 99% classification accuracy with 0.46 mJ/classification. For the second SCNN model with temporal coding scheme, the proposed architecture obtains a classification accuracy over 95.4% with 7.4 uJ/classification. Experimental results demonstrate that the proposed design is adaptable and has a low power consumption overhead.
TL;DR: In this paper , the performance of deep convolutional spiking neural networks (DCSNNs) trained using spike-based backpropagation techniques was investigated for object classification tasks.
Abstract: This paper investigates the performance of deep convolutional spiking neural networks (DCSNNs) trained using spike-based backpropagation techniques. Specifically, the study examined temporal spike sequence learning via backpropagation (TSSL-BP) and surrogate gradient descent via backpropagation (SGD-BP) as effective techniques for training DCSNNs on the field programmable gate array (FPGA) platform for object classification tasks. The primary objective of this experimental study was twofold: (i) to determine the most effective backpropagation technique, TSSL-BP or SGD-BP, for deeper spiking neural networks (SNNs) with convolution filters across various datasets; and (ii) to assess the feasibility of deploying DCSNNs trained using backpropagation techniques on low-power FPGA for inference, considering potential configuration adjustments and power requirements. The aforementioned objectives will assist in informing researchers and companies in this field regarding the limitations and unique perspectives of deploying DCSNNs on low-power FPGA devices. The study contributions have three main aspects: (i) the design of a low-power FPGA board featuring a deployable DCSNN chip suitable for object classification tasks; (ii) the inference of TSSL-BP and SGD-BP models with novel network architectures on the FPGA board for object classification tasks; and (iii) a comparative evaluation of the selected spike-based backpropagation techniques and the object classification performance of DCSNNs across multiple metrics using both public (MNIST, CIFAR10, KITTI) and private (INHA_ADAS, INHA_KLP) datasets.
References
More filters
12 Jul 2015
TL;DR: In this paper, a set of optimization techniques to minimize performance loss in the conversion process for convolutional networks and fully connected deep networks are presented, which yield networks that outperform all previous SNNs on the MNIST database.
Abstract: Deep neural networks such as Convolutional Networks (ConvNets) and Deep Belief Networks (DBNs) represent the state-of-the-art for many machine learning and computer vision classification problems To overcome the large computational cost of deep networks, spiking deep networks have recently been proposed, given the specialized hardware now available for spiking neural networks (SNNs) However, this has come at the cost of performance losses due to the conversion from analog neural networks (ANNs) without a notion of time, to sparsely firing, event-driven SNNs Here we analyze the effects of converting deep ANNs into SNNs with respect to the choice of parameters for spiking neurons such as firing rates and thresholds We present a set of optimization techniques to minimize performance loss in the conversion process for ConvNets and fully connected deep networks These techniques yield networks that outperform all previous SNNs on the MNIST database to date, and many networks here are close to maximum performance after only 20 ms of simulated time The techniques include using rectified linear units (ReLUs) with zero bias during training, and using a new weight normalization method to help regulate firing rates Our method for converting an ANN into an SNN enables low-latency classification with high accuracies already after the first output spike, and compared with previous SNN approaches it yields improved performance without increased training time The presented analysis and optimization techniques boost the value of spiking deep networks as an attractive framework for neuromorphic computing platforms aimed at fast and efficient pattern recognition
731 citations
TL;DR: This review addresses the opportunities that deep spiking networks offer and investigates in detail the challenges associated with training SNNs in a way that makes them competitive with conventional deep learning, but simultaneously allows for efficient mapping to hardware.
Abstract: Spiking neural networks (SNNs) are inspired by information processing in biology, where sparse and asynchronous binary signals are communicated and processed in a massively parallel fashion. SNNs on neuromorphic hardware exhibit favorable properties such as low power consumption, fast inference, and event-driven information processing. This makes them interesting candidates for the efficient implementation of deep neural networks, the method of choice for many machine learning tasks. In this review, we address the opportunities that deep spiking networks offer and investigate in detail the challenges associated with training SNNs in a way that makes them competitive with conventional deep learning, but simultaneously allows for efficient mapping to hardware. A wide range of training methods for SNNs is presented, ranging from the conversion of conventional deep networks into SNNs, constrained training before conversion, spiking variants of backpropagation, and biologically motivated variants of STDP. The goal of our review is to define a categorization of SNN training methods, and summarize their advantages and drawbacks. We further discuss relationships between SNNs and binary networks, which are becoming popular for efficient digital hardware implementation. Neuromorphic hardware platforms have great potential to enable deep spiking networks in real-world applications. We compare the suitability of various neuromorphic systems that have been developed over the past years, and investigate potential use cases. Neuromorphic approaches and conventional machine learning should not be considered simply two solutions to the same classes of problems, instead it is possible to identify and exploit their task-specific advantages. Deep SNNs offer great opportunities to work with new types of event-based sensors, exploit temporal codes and local on-chip learning, and we have so far just scratched the surface of realizing these advantages in practical applications.
511 citations
"EASpiNN: Effective Automated Spikin..." refers background in this paper
...Spiking neural network (SNN), known as the third-generation neural network, incorporates timing information in the network and is more biologically plausible [1]....
[...]
01 Apr 2018
TL;DR: It is found that for 6 out of the 15 ported kernels, today's FPGAs can provide comparable performance or even achieve better performance than the GPU, while consuming an average of 28% of the GPU power.
Abstract: This paper aims to better understand the performance differences between FPGAs and GPUs. We intentionally begin with a widely used GPU-friendly benchmark suite, Rodinia, and port 15 of the kernels onto FPGAs using HLS C. Then we propose an analytical model to compare their performance. We find that for 6 out of the 15 ported kernels, today's FPGAs can provide comparable performance or even achieve better performance than the GPU, while consuming an average of 28% of the GPU power. Besides lower clock frequency, FPGAs usually achieve a higher number of operations per cycle in each customized deep pipeline, but lower effective parallel factor due to the far lower off-chip memory bandwidth. With 4x more memory bandwidth, 8 out of the 15 FPGA kernels are projected to achieve at least half of the GPU kernel performance.
89 citations
Additional excerpts
...the loop pipelining and parallelization techniques for major computing engines [3]....
[...]