Effect of gate dielectric thickness on gate leakage in tunnel field effect transistor
14 Mar 2012-pp 1-4
TL;DR: In this article, the effect of gate dielectric thickness on gate leakage in tunnel FETs was simulated using two dimensional numerical simulations, and it was found that gate leakage is the most important component of off-state current and should be considered in future TFET device design.
Abstract: Gate leakage is one of the important parameter expected to limit the performance of Tunnel FETs. We have simulated the effect of gate dielectric thickness on gate leakage in Tunnel FETs, using two dimensional numerical simulations. It has been observed that gate leakage considerably affects the subthreshold characteristics of TFETs. It was found to be most important component of off-state current and should be considered in future TFET device design. Effects of gate metal workfunction on device characteristics, particularly, gate leakage and origin of reverse tunneling at drain have also been discussed.
Citations
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TL;DR: In this article, the authors present the recent progress of polymer dielectrics for high-performance field effect transistors (OFETs) applications and highlight the recent advances in polymer-based dielectric by classifying and comparing different categories of polymeric materials as well as polymer nanocomposites.
Abstract: Polymer-based gate dielectrics have received growing attention due to their important role in field-effect transistors (OFETs). This review article aims to present the recent progress of polymer dielectrics for high-performance OFET applications. We first discuss the requirements for polymer dielectrics in tailoring the overall performance of OFETs from the perspective of both bulk material properties and surface characteristics of the polymers. On this basis, we introduce the design strategies and desired processing techniques of polymer dielectrics for optimizing the charge transport and stabilizing the operation of OFETs. Then, we highlight the recent advances in polymer-based dielectrics by classifying and comparing different categories of polymeric materials as well as polymer nanocomposites, and focus is also given to elucidating the critical relationships between polymer structures, gate dielectric properties and OFET performance. Finally, a perspective of future research directions and challenges ...
108 citations
TL;DR: In this article, the effect of non-uniform gate oxide thickness on the current as well as the high-frequency performance of TFETs was investigated, and the effect was demonstrated by using a taper shape gate oxide.
Abstract: Gate dielectric scaling is a vital key to improve the steep switching characteristics of TFETs. However, scaling down the oxide thickness causes high gate leakage current that cannot be neglected. The impact of the leakage current on the device operation can cause a serious reliability problem. In this paper, we have investigated the effect of nonuniform gate oxide thickness on the current as well as the high-frequency performance of TFETs. The focus of this paper is to demonstrate how to reduce effects of gate leakage current by using a taper shape gate oxide. The IV and CV characteristics are investigated regarding different nonuniform gate oxide graded shapes. Further, the ON and OFF currents and SS, as figures of merit for low standby power application, have been analyzed. Apart from this, the RF figure of merit in terms of unit-gain cutoff frequency (fT) is investigated.
19 citations
01 Jan 2016
TL;DR: Tunnel Field Effect Transistors (TFETs) are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current.
Abstract: In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/ decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).
9 citations
TL;DR: In this paper, the authors investigated the device physics and design of point-tunneling TFETs with symmetric doping profiles and showed that the on-current is doubled due to an additional source and the ambipolar off-leakage is significantly diminished because the drain tunnel junction is designed far from the gate.
2 citations
References
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TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
2,390 citations
"Effect of gate dielectric thickness..." refers background or methods in this paper
...SOI based TFET has emerged as one of the most suitable candidates for future low power, low voltage devices [2], [3], [8-11]....
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...different injection mechanisms, such as Tunnel FET (TFET) [2], [3], Impact ionization (I-MOS) based FET, Resonant Gate Transistor, NEMFET, Ferroelectric negative capacitance [4-7]...
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29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
2,281 citations
"Effect of gate dielectric thickness..." refers background in this paper
...With reducing tox, gate dielectric leakage through thin oxide increases considerably and becomes the most important contributors of IOFF [13]....
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25 Oct 2010
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.
1,389 citations
"Effect of gate dielectric thickness..." refers background in this paper
...SOI based TFET has emerged as one of the most suitable candidates for future low power, low voltage devices [2], [3], [8-11]....
[...]
...different injection mechanisms, such as Tunnel FET (TFET) [2], [3], Impact ionization (I-MOS) based FET, Resonant Gate Transistor, NEMFET, Ferroelectric negative capacitance [4-7]...
[...]
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Abstract: In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
1,230 citations
TL;DR: In this paper, the resonant gate transistor (RGT) is described as an electrostatically excited tuning fork employing field effect transistor readout, which can be batch-fabricated in a manner consistent with silicon technology.
Abstract: A device is described which permits high- Q frequency selection to be incorporated into silicon integrated circuits. It is essentially an electrostatically excited tuning fork employing field-effect transistor "readout." The device, which is called the resonant gate transistor (RGT), can be batch-fabricated in a manner consistent with silicon technology. Experimental RGT's with gold vibrating beams operating in the frequency range 1 kHz 0 Q 's as high as 500 and overall input-output voltage gain approaching + 10 dB have been constructed. The mechanical and electrical operation of the RGT is analyzed. Expressions are derived for both the beam and the detector characteristic voltage, the device center frequency, as well as the device gain and gain-stability product. A batch-fabrication procedure for the RGT is demonstrated and theory and experiment corroborated. Both single- and multiple-pole pair band pass filters are fabricated and discussed. Temperature coefficients of frequency as low as 90- 150 ppm/°C for the finished batch-fabricated device were demonstrated.
1,143 citations
"Effect of gate dielectric thickness..." refers methods in this paper
...different injection mechanisms, such as Tunnel FET (TFET) [2], [3], Impact ionization (I-MOS) based FET, Resonant Gate Transistor, NEMFET, Ferroelectric negative capacitance [4-7]...
[...]