scispace - formally typeset
Search or ask a question
Journal ArticleDOI

Effect of Germanium Preamorphization Implant on Performance and Gate-Induced Drain Leakage in SiGe Channel pFET

17 Apr 2015-IEEE Electron Device Letters (IEEE)-Vol. 36, Iss: 6, pp 531-533
TL;DR: In this paper, the effect of prehalo/LDD Ge preamorphization implant (PAI) on gate-induced drain leakage (GIDL) and performance is investigated using experimental data and simulations.
Abstract: Silicon-germanium (SiGe) channel pMOSFET is considered as a replacement for silicon channel device for 32-nm node and beyond, because of its lower threshold voltage and higher channel mobility. Lower SiGe bandgap makes gate-induced drain leakage (GIDL) important for low leakage, high threshold voltage device designs. In this letter, the effect of prehalo/LDD Ge preamorphization implant (PAI) on GIDL and performance is investigated using experimental data and simulations. Results suggest that GIDL reduction of $\sim 40$ % is achieved without Ge PAI and the total off-state leakage $( {I}_{{\mathrm{{\scriptscriptstyle OFF}}}})$ is reduced by $\sim 50$ % with a slight reduction in drive current $( {I}_{{\mathrm{{\scriptscriptstyle ON}}}} )$ and similar short-channel effects as compared with the case with PAI for same process conditions, which is not reported yet. The reduction in GIDL, and hence the improvement in ${I}_{{\mathrm{{\scriptscriptstyle ON}}}}/\!{I}_{{\mathrm{{\scriptscriptstyle OFF}}}}$ ratio is because of elimination of end-of-range defects at the source/drain sidewall junction regions. It is also shown that a slight reduction in ${I}_{{\mathrm{{\scriptscriptstyle ON}}}}$ in the absence of Ge PAI is because of a small increase in the extrinsic series resistance.
Citations
More filters
Proceedings ArticleDOI
23 Mar 2017
TL;DR: In this paper, a silicon-germanium (SiGe) n-channel heterojunction MOSFET is presented under the consideration that channel is made of SiGe and source/drain regions are made of Silicon (Si). Bandgap engineering has been done to improve the electrical behavior of the device.
Abstract: In this paper, a silicon-germanium (SiGe) n-channel heterojunction MOSFET is presented under the consideration that channel is made of SiGe and source/drain regions is made of Silicon (Si). Bandgap engineering has been done to improve the electrical behavior of the device. Simulation work for different parameters on the device has been carried out and presented in the paper. The electrical characteristics of the proposed device is optimized by varying the device dimensions. Effect of mole fraction on threshold voltage (VT), Subthreshold swing (SS), ION and IOFF Current ratio is analyzed. It is seen that due to presence of SiGe channel, the proposed device shows enhancement in electrical characteristics.

4 citations

Journal ArticleDOI
TL;DR: In this paper, the gate-induced drain leakage (GIDL) is considered for high threshold voltage device design because of tunneling at reduced bandgap and trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe p-type FETs.
Abstract: Silicon–germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

3 citations

Journal ArticleDOI
TL;DR: In this paper, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe p-type field effect transistor (pFET) process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random drain leakage and performance variations.
Abstract: Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ( $\text{V}_{T}$ ) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage ( ${I}_{ \mathrm{\scriptscriptstyle OFF}} $ ) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages.

1 citations


Cites background or methods from "Effect of Germanium Preamorphizatio..."

  • ...It has been reported in [14] that GIDL reduction of around 40% can be achieved by eliminating the use of Ge preamorphization implant (PAI) used before the halo/lightly doped drain (LDD)...

    [...]

  • ...It is also shown in [14] that the presence of Ge leads to the formation of end-of-range (EOR) defects, which also increases the electric field in the region below the SiGe channel....

    [...]

  • ...It has been shown in [14] that the EOR defects formed due to the use of Ge PAI at the drain sidewall junction contribute to additional GIDL and are eliminated by removing Ge PAI....

    [...]

  • ...Interestingly, it was observed that the removal of Ge PAI does not degrade SCE [similar VT and drain-induced barrier lowering (DIBL) roll-off] in SiGe channel pFET [14], whereas it was a key factor in controlling the SCE in Si channel pFETs [18]....

    [...]

Proceedings ArticleDOI
01 Dec 2016
TL;DR: In this paper, the effect of pre-halo Ge pre-amorphization impant (PAI) on gate-induced drain leakage (GIDL) and its reduction is investigated.
Abstract: Variability in the transistor parameters play a significant role in CMOS scaling to nanometer feature sizes. New channel materials such as silicon-germanium for pFET at 32nm and beyond are useful because of higher mobility and lower threshold voltage. However, gate-induced drain leakage (GIDL) is dominant in the total leakage and the use of germanium (Ge) may introduce additional variability sources. In this work, pre-halo Ge pre-amorphization impant (PAI) effect on systematic and random variability of GIDL and its reduction is investigated. We report that the elimination of Ge PAI from the process flow reduces GIDL and the effect of systematic variations but increases the static random GIDL variations in planar transistors based on high-k metal gate technology. However, the random GIDL variation difference associated with Ge PAI may change for scaled supply voltages.

Cites background from "Effect of Germanium Preamorphizatio..."

  • ...Also, the removal of Ge PAI does not degrade SCE in SiGe channel device but leads to severe degradation in Si channel [5]....

    [...]

  • ...It has been reported in [5] that the removal of pre-halo/LDD Ge PAI (process step show in the inset of Fig....

    [...]

Journal ArticleDOI
TL;DR: In this paper , the source lifetime of a Germanium implanter, with and without using hydrogen (H_2) as carrier gas are evaluated and two different H_2 source mixing methods that provide longer source lifetime are analyzed and compared.
Abstract: Pre-amorphization implant (PAI) is adopted in CMOS processing as this appears to be effective in achieving a shallower junction depth. Germanium implantations are widely used especially for LDD and HALO implant applications. In the semiconductor industry, Germanium Tetrafluoride (GeF_4) gas has been a prominent source material for PAI. This fluoride-based source material has posed major challenges due to several negative effects on the beam performance and source lifetime. In this paper, the source lifetime of a Germanium implanter, with and without using hydrogen (H_2) as carrier gas are evaluated. Two different H_2 source mixing methods that provide longer source lifetime are analyzed and compared. Graphical abstract
References
More filters
Proceedings ArticleDOI
17 Jun 2008
TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.
Abstract: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

115 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.
Abstract: Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

107 citations

Journal ArticleDOI
D. Fleury1, Antoine Cros1, G. Bidal1, Julien Rosa1, G. Ghibaudo1 
TL;DR: In this paper, the source/drain series resistance of MOSFETs is extracted in a way that the result is insensitive to effective length and mobility variations, and applied to 45-nm bulk and fully depleted SOI MOSFLETs with high-κ and metal gate, having channel length down to 22 nm.
Abstract: This letter demonstrates a new technique to extract the source/drain series resistance of MOSFETs. Unlike the well-known total resistance techniques, Rsd is extracted in a way that the result is insensitive to effective length and mobility variations. The technique has been successfully applied to 45-nm bulk and fully depleted SOI MOSFETs with high-κ and metal gate, having channel length down to 22 nm. The technique provides a high accuracy and allows fast measurements and statistical analysis.

74 citations


"Effect of Germanium Preamorphizatio..." refers methods in this paper

  • ...The S/D series resistance is obtained by the method described in [12]....

    [...]

Journal ArticleDOI
TL;DR: In this article, the impact of lateral doping abruptness in the source/drain extension region and the gate-extension overlap length on device performance was studied and the I/sub on/ (supernominal)-I/sub off/ (subnominal) plot, which takes into account statistical variations of gate length was proposed as a good metric for comparing different device technology designs.
Abstract: This paper presents a detailed study of the impact of lateral doping abruptness in the source/drain extension region and the gate-extension overlap length on device performance. Proper choice of the metric used to compare the different device designs is essential. Series resistance and threshold voltage roll-offs are shown to be incomplete measures of device performance that could lead to inconsistent lateral abruptness requirements. While series resistance is seen to improve with increasing junction abruptness, threshold voltage roll-off could be degraded by both lateral junctions that are too gradual and too abrupt - in contrast to the conventional scaling assumptions. The I/sub on/ (supernominal)-I/sub off/ (subnominal) plot, which takes into account statistical variations of gate length, is proposed as a good metric for comparing different device technology designs. Gate-extension overlap length is shown to interact with lateral doping abruptness and to have a significant impact on device performance.

62 citations


"Effect of Germanium Preamorphizatio..." refers background in this paper

  • ...Lateral abruptness that is too gradual or too abrupt results in degraded VT behavior due to counter doping and charge sharing [4]....

    [...]

  • ...However, the earlier studies on Si channel without Ge PAI report degradation in short channel effects and ON current (IO N ) due to change in lateral abruptness near the extension region [4]....

    [...]

Proceedings ArticleDOI
12 Jun 2007
TL;DR: In this paper, a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.
Abstract: Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.

58 citations


"Effect of Germanium Preamorphizatio..." refers background in this paper

  • ...S ILICON-GERMANIUM (SiGe) is a promising channel material for pMOSFETs for 32nm and beyond in a high-k metal gate technology because of lower threshold voltage and higher mobility than in corresponding silicon (Si) channel device [1]....

    [...]