Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability
01 Dec 2018-
TL;DR: A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented in this paper.
Abstract: A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented. The study considers the random variation of ferroelectric remnant polarization $(\boldsymbol{P_{r}})$ and the presence of dielectric phases. In order to keep the ferroelectric-film induced device variability less than those induced by other sources (RDF, GER, FER, and MGG), we found that the DE content must be less than 20%, which is theoretically possible, and the grain to grain $\boldsymbol{P_{r}}$ variations less than 27%. While uniform single-crystalline ferroelectric film would provide the least device variation, we found 4 nm grains to produce less device variability than 5.3 nm grains due to the larger number of grains in the channel area.
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TL;DR: A new approach using multi-layer FE to engineer the shape of negative-capacitance field-effect transistor is discussed, and the results show that it leads to better sub-threshold swing as well as lower power supply.
Abstract: Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance ( ${C}_{\textsf {fe}}$ ) and the underlying MOS transistor ( ${C}_{\textsf {MOS}}$ ). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$ . The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor.
65 citations
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TL;DR: In this paper, the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the Ferroelectric field effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations was investigated.
Abstract: This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.
49 citations
Cites background from "Effect of Polycrystallinity and Pre..."
...phases that may form dielectric (DE) as merely high-k oxide [7], [8]....
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TL;DR: Results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability.
Abstract: In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.
44 citations
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TL;DR: In this article, the spacer design of the negative-capacitance FinFET (NC-FinFET) was investigated by using Sentaurus technology computer-aided design (TCAD).
Abstract: The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance.
35 citations
Additional excerpts
...The ON current of NCFET is boosted via a ferroelectric (FE) layer sandwiched by metal gate and dielectric layer, which is fully compatible with standard MOSFET or FinFET [2]–[6]....
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TL;DR: This work performed a correlative study with four scanning probe techniques for the local sensing of intrinsic ferroelectricity on the oxide surface, and demonstrated that different origins of spatially resolved contrast can be obtained, thus highlighting possible crosstalk not originated by a genuine ferro electric response.
Abstract: The ability to develop ferroelectric materials using binary oxides is critical to enable novel low-power, high-density non-volatile memory and fast switching logic. The discovery of ferroelectricity in hafnia-based thin films, has focused the hopes of the community on this class of materials to overcome the existing problems of perovskite-based integrated ferroelectrics. However, both the control of ferroelectricity in doped-HfO2 and the direct characterization at the nanoscale of ferroelectric phenomena, are increasingly difficult to achieve. The main limitations are imposed by the inherent intertwining of ferroelectric and dielectric properties, the role of strain, interfaces and electric field-mediated phase, and polarization changes. In this work, using Si-doped HfO2 as a material system, we performed a correlative study with four scanning probe techniques for the local sensing of intrinsic ferroelectricity on the oxide surface. Putting each technique in perspective, we demonstrated that different origins of spatially resolved contrast can be obtained, thus highlighting possible crosstalk not originated by a genuine ferroelectric response. By leveraging the strength of each method, we showed how intrinsic processes in ultrathin dielectrics, i.e., electronic leakage, existence and generation of energy states, charge trapping (de-trapping) phenomena, and electrochemical effects, can influence the sensed response. We then proceeded to initiate hysteresis loops by means of tip-induced spectroscopic cycling (i.e., “wake-up”), thus observing the onset of oxide degradation processes associated with this step. Finally, direct piezoelectric effects were studied using the high pressure resulting from the probe’s confinement, noticing the absence of a net time-invariant piezo-generated charge. Our results are critical in providing a general framework of interpretation for multiple nanoscale processes impacting ferroelectricity in doped-hafnia and strategies for sensing it.
14 citations
Cites background from "Effect of Polycrystallinity and Pre..."
...The understanding of these aspects can provide a correct physical picture of domain growth dynamics, fatigue and wake-up effects, a full understanding of which would enable a reduction in device variability [21,22]....
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