Journal ArticleDOI
Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)
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TLDR
In this paper, a threshold voltage model of short channel silicon-on-insulator (SOI) junctionless field effect transistors (JLFETs) has been presented, which includes the effect of substrate induced surface potential (SISP) effect on threshold voltage with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface.Abstract:
In the present paper, a threshold voltage model of short channel silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) has been presented. The model includes the effect of substrate-induced surface potential (SISP) effect on threshold voltage with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. Such changes render difference in potential between substrate bulk and surface. The channel potential has been modelled using the parabolic approximation method. The developed model is useful for the optimization of short-channel effects for SOI JLFETs. The substrate bias voltage as a fourth terminal is found to be a powerful tool for tuning the threshold voltage for different device parameters variation. The model results are in good agreement with the simulation results obtained from Sentaurus TCAD simulator.read more
Citations
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Journal ArticleDOI
Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs
TL;DR: In this paper, the analytical modeling of threshold voltage of an ultra-thin nanotube junctionless double-gate-all-around (NJL-DGAA) metal-oxide-semiconductor field effect transistor (MOSFET) was presented.
Proceedings ArticleDOI
Analytical Model Development for Channel Potential in Junction-less Double-Gate FETs
TL;DR: In this paper, an analytical model for potential distribution in channel region of junctionless-double-gate FETs by considering Gaussian-like vertical doping is introduced, where the channel potential considered to be the addition of the conventional device potential obtained by Poisson's solution and the potential function calculated by Laplace equation.
Journal ArticleDOI
Back Bias Induced Modeling of Subthreshold Characteristics of SOI Junctionless Field Effect Transistor (JLFET)
TL;DR: In this article, the subthreshold swing characteristics of asymmetric silicon-on-insulator (SOI) junctionless field effect transistors (JLFETs) were investigated by formulating the sub-threshold SW characteristics based on the minimum potential concept.
Proceedings ArticleDOI
Threshold-Voltage Analytical-Model Development for Junction-less-Double-Gate FETs
TL;DR: In this article, a threshold voltage analytical model for junctionless double-gate FETs by considering Gaussian-like vertical doping is presented, where the channel potential is considered to be the addition of the conventional device potential obtained by Poisson's solution.
Journal ArticleDOI
CJFET Differential Pairs’ Constructions and Characteristics for Design of Cbicjfet Differential Amplifiers and Differential Difference Amplifiers’
E. M. Savchenko,Dmitry G. Drozdov,V. G. Rodin,А. I. Grushin,P. А. Dukanov,Nikolay N. Prokopenko +5 more
TL;DR: In this article, the authors present the results of experimental studies of two types of DP JFet designs with p-and n-channels for the spread of gatesource voltage ΔVGS depending on the drain current and drain-source voltage.
References
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Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI
Frontiers of silicon-on-insulator
TL;DR: In this article, the authors discuss methods of forming silicon-on-insulator (SOI) wafers, their physical properties, and the latest improvements in controlling the structure parameters.
Journal ArticleDOI
A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs
TL;DR: An analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time in this article, which explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation.
Journal ArticleDOI
Realizing Efficient Volume Depletion in SOI Junctionless FETs
TL;DR: A simple and effective solution to realize efficient volume depletion and therefore, significantly reduce the OFF-state leakage current of a junctionless FET (JLFET) by replacing the SiO 2 by HfO 2 in the buried oxide (BOX).
Journal ArticleDOI
Analytical Modeling of Channel Potential and Threshold Voltage of Double-Gate Junctionless FETs With a Vertical Gaussian-Like Doping Profile
TL;DR: In this article, an analytical 2D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile was proposed.
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