Journal ArticleDOI
Effective built-in self test for Booth multipliers
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This generic BIST scheme does not require DFT modifications in the multiplier structure, guarantees fault coverage higher than 99%, and can be adopted by any module generator.Abstract:
Booth multipliers, widely used as embedded cores in general-purpose data path structures and specialized digital signal processors, pose serious testability problems This generic BIST scheme does not require DFT modifications in the multiplier structure, guarantees fault coverage higher than 99%, and can be adopted by any module generatorread more
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Book
System-on-Chip Test Architectures: Nanometer Design for Testability
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Proceedings ArticleDOI
Low power/energy BIST scheme for datapaths
TL;DR: This work proposes low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns, and finds that these schemes are more efficient than pseudorandom BIST for the same high fault coverage target.
Proceedings ArticleDOI
Deterministic software-based self-testing of embedded processor cores
TL;DR: A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure to provide high fault coverage without repetitive fault simulation experiments.
Proceedings ArticleDOI
Effective Software Self-Test Methodology for Processor Cores
TL;DR: This work introduces an efficient methodology for processor cores self-testing which requires knowledge of their instruction set and Register Transfer (RI) level description and is more efficient in terms of fault coverage, test code size and test application time.
Journal ArticleDOI
Easily Testable Cellular Carry Lookahead Adders
TL;DR: This paper proposes DFT modifications for cellular CLA adders to achieve complete CFM testability with special emphasis on the minimum impact in terms of area and performance, providing a practical solution.
References
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Journal ArticleDOI
Serial interfacing for embedded-memory testing
TL;DR: A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented, which requires only two serial pins for access to the data path for external testing.
Journal ArticleDOI
Test responses compaction in accumulators with rotate carry adders
Janusz Rajski,Jerzy Tyszer +1 more
TL;DR: An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is presented, and it is shown that the asymptotic coverage drop depends both on the size of the accumulator and the probability of a fault injection.
Journal ArticleDOI
Built-in self-test for digital integrated circuits
TL;DR: The basic approaches of built-in self-test (BIST) are introduced and different attributes of BIST schemes, their tradeoffs and available tools are presented, and a practical application of the schemes described is demonstrated.
Journal ArticleDOI
An effective BIST scheme for ROM's
Yervant Zorian,André Ivanov +1 more
TL;DR: A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described.
Proceedings ArticleDOI
Test response compaction using arithmetic functions
TL;DR: This paper analyzes aliasing in registers and adders, subtracters, or arithmetic logic units when the test responses of circuits with arbitrary combinational faults are compacted, and gives the limiting values that the aliasing probability tends to for increasing test lengths.