Efficient FPGA-based karatsuba multipliers for polynomials over F 2
11 Aug 2005-pp 359-369
TL;DR: In this paper, different possibilities of implementing the Karatsuba multiplier for polynomials over FPGAs are investigated. But the authors focus on the problem of implementing finite fields of characteristic 2.
Abstract: We study different possibilities of implementing the Karatsuba multiplier for polynomials over ${\mathbb F}_{2}$ on FPGAs.
This is a core task for implementing finite fields of characteristic 2. Algorithmic and platform dependent optimizations yield efficient hardware designs. The resulting structure is hybrid in two different aspects. On the one hand, a combination of the classical and the Karatsuba methods decreases the number of bit operations. On the other hand, a mixture of sequential and combinational circuit design techniques includes pipelining and can be adapted flexibly to time-area constraints. The approach—both theory and implementation—can be viewed as a further step towards taming the machinery of fast algorithmics for hardware applications.
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07 Oct 2012
TL;DR: This work makes a first step towards efficient FFT-based arithmetic for lattice-based cryptography and shows that the FFT can be implemented efficiently on reconfigurable hardware.
Abstract: In recent years lattice-based cryptography has emerged as quantum secure and theoretically elegant alternative to classical cryptographic schemes (like ECC or RSA). In addition to that, lattices are a versatile tool and play an important role in the development of efficient fully or somewhat homomorphic encryption (SHE/FHE) schemes. In practice, ideal lattices defined in the polynomial ring ℤp[x]/〈xn+1〉 allow the reduction of the generally very large key sizes of lattice constructions. Another advantage of ideal lattices is that polynomial multiplication is a basic operation that has, in theory, only quasi-linear time complexity of ${\mathcal O}(n \log{n})$ in ℤp[x]/〈xn+1〉. However, few is known about the practical performance of the FFT in this specific application domain and whether it is really an alternative. In this work we make a first step towards efficient FFT-based arithmetic for lattice-based cryptography and show that the FFT can be implemented efficiently on reconfigurable hardware. We give instantiations of recently proposed parameter sets for homomorphic and public-key encryption. In a generic setting we are able to multiply polynomials with up to 4096 coefficients and a 17-bit prime in less than 0.5 milliseconds. For a parameter set of a SHE scheme (n=1024,p=1061093377) our implementation performs 9063 polynomial multiplications per second on a mid-range Spartan-6.
157 citations
TL;DR: This work presents a new scheme for subquadratic space complexity parallel multiplication in GF(2n) using the shifted polynomial basis using the Toeplitz matrix-vector products and coordinate transformation techniques, and to the best of the authors' knowledge, this is the first time that sub quadraticspace complexity parallel multipliers are proposed for dual, weakly dual, and triangular bases.
Abstract: Based on Toeplitz matrix-vector products and coordinate transformation techniques, we present a new scheme for subquadratic space complexity parallel multiplication in GF(2n) using the shifted polynomial basis. Both the space complexity and the asymptotic gate delay of the proposed multiplier are better than those of the best existing subquadratic space complexity parallel multipliers. For example, with n being a power of 2, the space complexity is about 8 percent better, while the asymptotic gate delay is about 33 percent better, respectively. Another advantage of the proposed matrix-vector product approach is that it can also be used to design subquadratic space complexity polynomial, dual, weakly dual, and triangular basis parallel multipliers. To the best of our knowledge, this is the first time that subquadratic space complexity parallel multipliers are proposed for dual, weakly dual, and triangular bases. A recursive design algorithm is also proposed for efficient construction of the proposed subquadratic space complexity multipliers. This design algorithm can be modified for the construction of most of the subquadratic space complexity multipliers previously reported in the literature
141 citations
TL;DR: In this survey, techniques for implementing Elliptic Curve Cryptography at a high-speed are explored and a classification of the work available in the open literature in function of the level of efficiency and flexibility is proposed.
117 citations
TL;DR: In this paper, a simple way to split input operands allows for fast VLSI implementations of subquadratic GF (2)[x ] Karatsuba-Ofman multipliers.
Abstract: The authors describe how a simple way to split input operands allows for fast VLSI implementations of subquadratic GF (2)[ x ] Karatsuba-Ofman multipliers. The theoretical XOR gate delay of the resulting multipliers is reduced significantly. For example, it is reduced by about 33 and 25% for n = 2 t and n = 3 t ( t > 1), respectively. To the best of our knowledge, this parameter has never been improved since the original Karatsuba-Ofman algorithm was first used to design GF (2 n ) multipliers in 1990.
62 citations
TL;DR: This paper introduces the common expression sharing and the complexity analysis on odd-term polynomials to achieve a lower gate bound than previous ASIC discussions and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers over GF(2m) .
Abstract: This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2m) . By introducing the common expression sharing and the complexity analysis on odd-term polynomials, we achieve a lower gate bound than previous ASIC discussions. The analysis is extended by using 4-input/6-input lookup tables (LUT) on FPGAs. For an arbitrary bit-depth, the optimum iteration step is shown. The optimum iteration steps differ for ASICs, 4-input LUT-based FPGAs and 6-input LUT-based FPGAs. We evaluate the LUT complexity and area-time product tradeoffs on FPGAs with different computer-aided design (CAD) tools. Furthermore, the experimental results on FPGAs for bit parallel modular multipliers are shown and compared with previous implementations. To the best of our knowledge, our bit parallel multipliers consume the least resources among known FPGA implementations to date.
53 citations
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