Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding
01 May 2016-pp 1-6
TL;DR: The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter, which provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly.
Abstract: In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of parallelization. However, the hardware complexity of adders and multipliers rises quadratically with parallelization factor. In our proposed technique, we have used look-up table (LUT) and shift-accumulate block as per DA requirement. In order to reduce the access time of LUT, we employed OBC scheme which therefore improves the speed of filtering operation. Moreover, it also reduces the chip area for LUT based filter design. Furthermore, our design provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly. By doing so, the concurrent nature of look-ahead DFE is unaltered and can still be used for multi-gigabit applications. We have estimated hardware complexity and critical path of our design and compared with best existing schemes. Synthesis is performed in UMC 180 nm CMOS technology using cadence RTL compiler for the feedback filter length N = 4, 6 and 8. The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter.
Citations
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TL;DR: The proposed NMLDA based DFE has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.
Abstract: In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.
20 citations
TL;DR: Simulation results show that the convergence characteristics of the proposed DA based LMS ADFE is almost similar to conventional multiply-accumulate (MAC) based realization.
References
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01 Mar 19912,447 citations
"Efficient implementation of concurr..." refers methods in this paper
...INTRODUCTION Decision feedback equalizer is widely used in channel equalization [1]....
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TL;DR: It is shown that practical implementations of DA adaptive filters have very high throughput relative to multiply and accumulate architectures and have a potential area and power consumption advantage over digital signal processing microprocessor architectures.
Abstract: We present a new hardware adaptive filter architecture for very high throughput LMS adaptive filters using distributed arithmetic (DA). DA uses bit-serial operations and look-up tables (LUTs) to implement high throughput filters that use only about one cycle per bit of resolution regardless of filter length. However, building adaptive DA filters requires recalculating the LUTs for each adaptation which can negate any performance advantages of DA filtering. By using an auxiliary LUT with special addressing, the efficiency and throughput of DA adaptive filters can be of the same order as fixed DA filters. In this paper, we discuss a new hardware adaptive filter structure for very high throughput LMS adaptive filters. We describe the development of DA adaptive filters and show that practical implementations of DA adaptive filters have very high throughput relative to multiply and accumulate architectures. We also show that DA adaptive filters have a potential area and power consumption advantage over digital signal processing microprocessor architectures.
146 citations
"Efficient implementation of concurr..." refers methods in this paper
...in [10] have included the weight updating block using an extra LUT, throughput of which is constant regardless of the filter length....
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TL;DR: This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD).
Abstract: This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD). This is the first MLSD-based transceiver for multimode fibers and the first fully integrated DSP based transceiver for optical channels reported in the technical literature. The digital receiver incorporates equalization, Viterbi detection, channel estimation, timing recovery, and gain control functions. The analog front-end incorporates an 8-way interleaved ADC with self-calibration, a programmable gain amplifier, a phase interpolator, and the transmitter. Also integrated are a XAUI interface, the physical coding sublayer (PCS), and miscellaneous test and control functions. Experimental results using the stressors specified by the IEEE 10 GBASE-LRM standard, as well as industry-defined worst-case fibers are reported. A sensitivity of - 13.68 dBm is demonstrated for the symmetric stressor in a line card application with a 6 inch FR4 interconnect.
84 citations
"Efficient implementation of concurr..." refers background in this paper
...Apart from all the aforementioned advantages its speed is limited due to iteration bound [2]....
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TL;DR: Two novel DA-based implementation schemes are proposed for adaptive finite-impulse response filters that achieve high speed, low computation complexities, and low area cost.
Abstract: Distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this brief, two novel DA-based implementation schemes are proposed for adaptive finite-impulse response filters. Different from conventional DA techniques, our proposed schemes use coefficients as addresses to access a series of lookup tables (LUTs) storing sums of delayed and scaled input samples. Two smart LUT updating methods are developed, and least-mean-square adaptation is performed to update the weights and minimize the mean square error between the estimated and desired output. Results show that our two high-performance designs achieve high speed, low computation complexities, and low area cost.
83 citations
"Efficient implementation of concurr..." refers methods in this paper
...Later, this work was improved by [11], [12] for a small area and high throughput realization of FIR adaptive filters....
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TL;DR: A high-performance implementation scheme for a least mean square adaptive filter based on a new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time.
Abstract: A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size k ( = N/m) , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8) and consumes almost 26% less area when compared to the best of existing architectures.
56 citations
"Efficient implementation of concurr..." refers methods in this paper
...Later, this work was improved by [11], [12] for a small area and high throughput realization of FIR adaptive filters....
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