Efficient Iterative Process Based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level
TL;DR: In this paper, a genetic algorithm is used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values.
Abstract: To reduce the noise created by a power delivery network, the number, the value of decoupling capacitors and their arrangement on the board are critical to reaching this goal. This work deals with specific improvements, implemented on a genetic algorithm, which used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values. Measurements are performed on a specifically manufactured board in order to validate the effectiveness of the proposed algorithm and the optimization results obtained for a specific example board.
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01 Jul 2020
TL;DR: An optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution is proposed, leading to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location.
Abstract: The current demand in Power Distribution Network (PDN) design is characterized by the accurate placement of decoupling capacitors and the minimization of their number aimed at cost saving. The paper proposes an optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution. This allows the designer to identify the minimum number of decaps whenever the input impedance satisfies the target impedance requirements. The algorithm is based on the Genetic Algorithm accordingly adapted for the specific application of PDN design. It may involve the evaluation of the input impedance at multiple locations, representing either multiple ICs, as well as multiple power input areas/pins of the same IC. The validation of the developed optimization algorithm is carried out by applying it to a manufactured PCB and by employing typical (low inductance) decaps for PDN design. The optimization process led to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location. An accurate experimental test further validates the optimized PDN.
17 citations
TL;DR: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm and Artificial Neural Network to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators.
Abstract: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm (GA) and Artificial Neural Network (ANN). The ANN is first trained by an appropriate set of results obtained by a commercial simulator. Once the ANN is ready, it is used within an iterative GA process to place a minimum number of decoupling capacitors for minimizing the differences between the input impedance at one or more location, and the required target impedance. The combined GA–ANN process is shown to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators. With the new approach the accuracy of the results remains at the same level, but the computational time is reduced by at least 30 times. Two test cases have been considered for validating the proposed approach, with the second one also being compared by experimental measurements.
12 citations
01 Jan 2016
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9 citations
26 Jul 2021
TL;DR: In this article, a new genetic algorithm (GA) is proposed for the selection and placement of capacitors to meet a target impedance using as few capacitors as possible, which is centered around controlling the number of unused port locations in the GA population solutions, with the result of smoothing out the GA convergence and speeding up the convergence rate.
Abstract: Decoupling capacitors are used to provide adequate and stable power for integrated circuits in printed circuit boards (PCB). For complicated and large designs, it is difficult to select capacitors to meet voltage ripple limits while also minimizing cost because the search space is too large. In this work, a new genetic algorithm (GA) is proposed for the selection and placement of capacitors to meet a target impedance using as few capacitors as possible. The GA is centered around controlling the number of unused port locations in the GA population solutions, with the result of smoothing out the GA convergence and speeding up the convergence rate. A result comparison is made of the proposed GA against other algorithms and found the GA competitive if not better for the select test cases.
2 citations
01 Jan 2023
TL;DR: In this article , an improved genetic algorithm was used to find the optimal digital economic dispatching system, so as to make up for the shortcomings of the classical genetic algorithm, which can be applied in many disciplines and has become a hot topic in interdisciplinary research.
Abstract: China has entered the stage of rapid economic development, and its comprehensive national strength has advanced by leaps and bounds. Digital technology not only promotes the digital transformation of traditional industries, but also drives the development of emerging industries. The development of digital economy has become the only way for economic development. Genetic algorithm is a highly abstract algorithm, which can be applied in many disciplines and has become a hot topic in interdisciplinary research. The purpose of this paper is to realize and optimize the digital economic dispatching system based on the improved genetic algorithm. In the experiment, through the comparison between the improved genetic algorithm and the standard algorithm, the improved genetic algorithm is used to find the optimal digital economic dispatching system, so as to make up for the shortcomings of the classical genetic algorithm.
References
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TL;DR: A genetic algorithm (GA)-based method is proposed for simultaneous optimization of decoupling capacitors assigned to multiple pins of a ball-grid array (BGA) package on a printed circuit board and a noise susceptibility parameter is introduced as the basis of a new set of GA fitness functions.
Abstract: A genetic algorithm (GA)-based method is proposed for simultaneous optimization of decoupling capacitors assigned to multiple pins of a ball-grid array (BGA) package on a printed circuit board. A noise susceptibility parameter is introduced as the basis of a new set of GA fitness functions. Performance of several fitness functions is comparatively tested and discussed in case studies. The accuracy of the developed expressions is tested against full-wave electromagnetic simulation results. The proposed method is particularly useful for predicting the number and placement of decoupling capacitors under the BGA area of integrated circuit devices in early design stages and serves as a complement to rigorous algorithms that are used in the final phase of the design.
27 citations
"Efficient Iterative Process Based o..." refers background in this paper
...Usually, the target impedance is flat over a wide range of frequency [6,15,17], leading to overdesign the PDN by adding more decaps than needed....
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01 May 2017
23 citations
"Efficient Iterative Process Based o..." refers methods in this paper
...The use of optimization algorithms [26,27], and, specifically, of genetic algorithm (GA) is widely spread for electromagnetic problems [28–31]....
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TL;DR: An approach based on the combination of time-domain contour integral method and optimization with variable number of dimensions is introduced and works with models having variable dimensions and searches for the optimal one.
Abstract: The decoupling of modern printed circuit boards introduces a very complex task. Powerful stochastic optimizers are usually used to determine values and positions of decoupling capacitors on the board. The number of capacitors used has to be determined a priori by the user which brings problems with convergence of the optimization process or can lead to a waste of resources when the noises are to be attenuated to a certain level. In this paper, an approach based on the combination of time-domain contour integral method and optimization with variable number of dimensions is introduced. The optimizer works with models having variable dimensions and searches for the optimal one. The approach is tested on two example power circuit boards with various noise attenuation limits and constraints on capacitor positions and values.
19 citations
01 Jan 2004
TL;DR: Zamek et al. as mentioned in this paper developed a methodology to model the FPGA dynamic current waveform and its spectrum using an impedance transfer function, which allows predicting noise at a remote point on the PCB.
Abstract: Dynamic current variations in FPGA or microprocessors are major characteristics for analyzing noise in a power delivery network (PDN). Direct measurement of FPGA dynamic current variation is a very difficult problem, and is less studied than other PDN design questions. In this paper, a methodology to model the FPGA dynamic current waveform and its spectrum is developed and presented. Implementation of an impedance transfer function allows predicting noise at a remote point on the PCB. Using modeling results, the noise waveform and spectrum in the PDN on the PCB is estimated. Measurements at the remote point on the PCB help evaluate the proposed methodology and show a good correlation between theory and experiments. This research demonstrates also the implementation of a dynamic current modeling methodology for PDN analysis and PCB decoupling design. Author Biographies Iliya Zamek, a member of technical staff at Altera Corporation, has over twenty years of experience with high-speed analog and digital circuits, memory, system design, project management, and products development. Besides developing testers and measurement methodology for FPGA characterization, he leads R&D projects on modeling jitter and dynamic current in FPGA and prediction noise in power distribution networks. Prior to Altera, he worked for U.S. crystal oscillator manufacturers Q-Tech and Statek Corp., and, earlier, the leading Russian instrumentation corporation, “Quartz.” He has BS and MS degrees in physics and electronics from Gorky University, and a PhD in measurement techniques. He has published more than 50 papers, including 12 patents, with six more pending. Peter Boyle received his BCE from the Georgia Institute of Technology in 1999. He currently works for Altera Corporation as a manager in the product engineering characterization group, where his group is responsible for measurement of I/Os, PLLs, external memory interface, and SSN. His interests include system-level measurement techniques and modeling. He has several inventions pending. Shishuang Sun received BS and MS degrees in electrical engineering from Shanghai Jiao Tong University, China, in 1999 and 2002, respectively, and a PhD degree in electrical engineering from the University of Missouri-Rolla in 2006. He currently works as a senior engineer in Altera Corporation’s product characterization group. His research interests include signal integrity in high-speed digital systems, and PDN design and modeling. Zhe Li is a product characterization engineer at Altera Corporation, where he works on characterization, modeling, and correlation of FPGAs. He received a MSEE from the University of Missouri-Rolla. His interests include signal integrity analysis and highspeed digital system design. He has published three papers and has two pending inventions. Daryl G. Beetner is an Associate Professor of Electrical and Computer Engineering at the University of Missouri-Rolla and is the associate chair of the Computer Engineering program. He received his B.S. degree in Electrical Engineering from Southern Illinois University at Edwardsville in 1990. He received an M.S. and D.Sc. degree in Electrical Engineering from Washington University in St Louis in 1994 and 1997, respectively. He conducts research on a wide range of topics including skin cancer detection, humanitarian demining, very large-scale integrated circuit design, and electromagnetic compatibility. He is a faculty member of the UMR Electromagnetic Compatibility Laboratory. James L. Drewniak (S’85–M’90–SM’01-F’07) received BS, MS, and PhD degrees in electrical engineering from the University of Illinois, Urbana-Champaign, in 1985, 1987, and 1991, respectively. He joined the Electrical Engineering Department, University of Missouri-Rolla, in 1991, where he is one of the principal faculty members in the Electromagnetic Compatibility Laboratory. His research and teaching interests include electromagnetic compatibility in high-speed digital and mixed-signal designs, electronic packaging, and electromagnetic compatibility in power electronic-based systems. Xiaohe Chen received a BS degree in computer science from Tsinghua University in 2000, and an MS in electrical engineering from Southern Illinois University Edwardsville in 2003. He is a current PhD candidate at University of Missouri-Rolla. His research interests include signal integrity in high-speed digital systems, and PDN design and electromagnetic modeling. Tun Li received a BS degree in electrical engineering from Shanghai Jiaotong University in 2004, and an MS in electrical engineering from Tsinghua University in 2006. She is currently a MS student at University of Missouri-Rolla. Her research interests include signal integrity in PDN design and immunity testing in near field probes. Sandeep Chandra received his BS degrees in electronics and communication engineering from Sri Krishna Deveraya University, India, in 2005.He is currently an MS student at University of Missouri-Rolla. His research interests include signal integrity in high-speed digital systems, PDN design, electromagnetic shielding, and electromagnetic modeling.
19 citations
"Efficient Iterative Process Based o..." refers background in this paper
...Modern approaches cannot disregard or ignore a correct and efficient design of the power delivery network (PDN) in order to decrease the transient noise caused by voltage droops, due to switching currents [8,9]....
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01 Oct 2007
TL;DR: Removal of members of population having certain percentage of similarity would keep GA perform better, balancing and maintaining convergence property intact as well as avoids stalling.
Abstract: The schemata theorem, on which the working of Genetic Algorithm (GA) is based in its current form, has a fallacious selection procedure and incomplete crossover operation. In this paper, generalization of the schemata theorem has been provided by correcting and removing these limitations. The analysis shows that similarity growth within GA population is inherent due to its stochastic nature. While the stochastic property helps in GA's convergence. The similarity growth is responsible for stalling and becomes more prevalent for hard optimization problem like protein structure prediction (PSP). While it is very essential that GA should explore the vast and complicated search landscape, in reality, it is often stuck in local minima. This paper shows that, removal of members of population having certain percentage of similarity would keep GA perform better, balancing and maintaining convergence property intact as well as avoids stalling.
18 citations
"Efficient Iterative Process Based o..." refers background or methods in this paper
...To avoid this trap, a twin removal routine introduced in References [32,33] has been introduced as a further improvement....
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...Together to this change in the optimization architecture, the GA developed in Reference [14] has been improved for a more effective and reliable process by adding the twin removal [32,33], and the binary coding of all inputs to increase the randomness of the configuration selection....
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...routine introduced in References [32,33] has been introduced as a further improvement....
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...Electronics 2019, 8, 1219 5 of 16 routine introduced in References [32,33] has been introduced as a further improvement....
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