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Journal ArticleDOI

Efficient Jitter Analysis for a Chain of CMOS Inverters

TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.
Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.
Citations
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Journal ArticleDOI
TL;DR: In this article, an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN) is presented, where the deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition.
Abstract: This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.

11 citations

Proceedings ArticleDOI
18 Jun 2019
TL;DR: In this paper, an assessment of jitter induced by power and ground (P/G) voltage variations is presented based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers.
Abstract: This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers. The requirements of nonlinear modeling for the accurate prediction is explained and illustrated. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum values of the prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

10 citations


Cites background or methods or result from "Efficient Jitter Analysis for a Cha..."

  • ...The achieved results of both approaches show a good agreement with the SPICE-based physical model in predicting the jitter induced by P/G voltage variations [3], [5]....

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  • ...Predicting the jitter induced by power and ground (P/G) noise fluctuations is important for signal and power integrity analysis of high-speed I/O links [1]-[3]....

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  • ...Therefore, a small signal transistor model for P/G induced jitter can be used by including the linear capacitive effects [3], [5]....

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  • ...time differences between the rising and falling transitions of the reference signal and that of distorted signal) of a driver consisting multiple cascaded inverters was derived based on the linear equivalent circuit of each CMOS inverter in [3], [4]....

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Proceedings ArticleDOI
26 May 2019
TL;DR: The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method and the mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).
Abstract: This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

7 citations


Cites methods from "Efficient Jitter Analysis for a Cha..."

  • ...Several analytical, semi-analytical, statistical and numerical methods are available in the literature for PSIJ analysis [7], [13]–[20]....

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Proceedings ArticleDOI
07 Mar 2019
TL;DR: The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained with full SPICE based simulations.
Abstract: This paper presents an analysis of jitter due to various deterministic noise sources in a CMOS inverter. The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained from full SPICE based simulations. For the estimation of jitter, EMPSIJ method [1] is used in the paper. The paper also discusses the sensitivity of various noise paths on jitter.

7 citations


Additional excerpts

  • ...sources in an inverter is presented in [10], where the analysis is done by considering three noise sources from the supply, the data input and the ground....

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Journal ArticleDOI
TL;DR: An efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources is presented.
Abstract: This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.

6 citations


Cites background or methods from "Efficient Jitter Analysis for a Cha..."

  • ...The timing analysis at the output of a delay-line or a tapered buffer in the presence of PSN can be performed using various methods [4], [6], [9]–[11], [14], [15]....

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  • ...A slope based semi-analytical approach for the estimation of PSIJ in CMOS inverter chains is presented in [14]....

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  • ...The magnitude and phase response at the output due to the power supply noise, ground bounce and data noise can be obtained by deriving the transfer functions from respective inputs to the output [14]....

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References
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Journal ArticleDOI
TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).
Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

45 citations


"Efficient Jitter Analysis for a Cha..." refers methods in this paper

  • ...A detailed review of PSIJ estimation techniques is presented in [17]....

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Journal ArticleDOI
TL;DR: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer from a linear differential equation obtained from asymptotic linear inverter I-V curves.
Abstract: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations.

44 citations

Proceedings ArticleDOI
R. Schmitt1, Hai Lan1, Chris Madden1, Chuck Yuan1
21 Nov 2007
TL;DR: In this article, a detailed analysis of supply noise induced jitter in a high-speed interface is presented, where the sensitivity of the interface circuits to noise is measured as a function of noise frequency.
Abstract: Minimizing the jitter due to supply noise is the most important design goal for the power delivery system of highspeed interfaces. We present a detailed analysis of supply noise induced jitter in a high-speed interface. We first simulate the supply noise spectrum generated in the interface. We then measure the sensitivity of the interface circuits to noise as a function of noise frequency. Next, we analyze the jitter spectrum by combining these two parameters. Based on this analysis, we observe large jitter contributions at medium frequencies. This is not expected if we consider only the supply noise current spectrum since the medium frequency is way below the data rate or the frequencies of internal clock signals. However, it can be easily explained with the power supply network impedance profile. Finally, we correlate the predicted jitter spectrum with the measured jitter spectrum of a serial link operating at 6.4 Gbps.

44 citations


"Efficient Jitter Analysis for a Cha..." refers methods in this paper

  • ...These approaches include statistical methods, such as probability density function (pdf) based method [11] and jitter sensitivity function based methods[15], [16]....

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Journal ArticleDOI
TL;DR: This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain.
Abstract: This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain. The transfer function is mainly a function of the maximum and minimum propagation delay of the buffer chain. The function can be easily obtained and used in jitter budget calculation.

35 citations


"Efficient Jitter Analysis for a Cha..." refers background in this paper

  • ...In [20] and [21], the same is analyzed for a chain of inverters where the transfer function from power supply to the output jitter of N -cascaded inverter stages is derived....

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Journal ArticleDOI
TL;DR: An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed and validated by comparisons with HSPICE and experimental results.
Abstract: An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-supply voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-supply voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).

33 citations


"Efficient Jitter Analysis for a Cha..." refers methods in this paper

  • ...These approaches include statistical methods, such as probability density function (pdf) based method [11] and jitter sensitivity function based methods[15], [16]....

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