Journal ArticleDOI
Efficient Jitter Analysis for a Chain of CMOS Inverters
Reads0
Chats0
TLDR
An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.Abstract:
This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.read more
Citations
More filters
Journal ArticleDOI
Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters
TL;DR: In this article, an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN) is presented, where the deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition.
Proceedings ArticleDOI
An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)
TL;DR: In this paper, an assessment of jitter induced by power and ground (P/G) voltage variations is presented based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers.
Proceedings ArticleDOI
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator
Vijender Kumar Sharma,B. Dinesh Kumar,Muhammed Suhail Illikkal,Jai Narayan Tripathi,Navneet Gupta,Hitesh Shrimali +5 more
TL;DR: The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method and the mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).
Proceedings ArticleDOI
Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter
TL;DR: The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained with full SPICE based simulations.
Journal ArticleDOI
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers
TL;DR: An efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources is presented.
References
More filters
Proceedings ArticleDOI
Analytical expressions for transfer function of supply voltage fluctuation to jitter at a single-ended buffer
TL;DR: The transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions and validated by comparison with HSPICE simulation.
Journal ArticleDOI
Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)
TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.
Journal ArticleDOI
Analytic Calculation of Jitter Induced by Power and Ground Noise Based on IBIS I/V Curve
TL;DR: The method is validated by comparing the analytic calculation results with HSPICE simulated results for a DDR4 output buffer, and the total time interval error induced by power and ground noise is obtained in both frequency domain and time domain.
Journal ArticleDOI
Precise Analytical Model of Power Supply Induced Jitter Transfer Function at Inverter Chains
TL;DR: The full PSIJ transfer function model is significantly simplified, which provides physical insights of PSIJ at inverter chains and is successfully validated by SPICE simulations with 130 nm CMOS technology.
Journal ArticleDOI
Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers
TL;DR: The proposed method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically.