Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)
03 Jul 2017-IEEE Transactions on Components, Packaging and Manufacturing Technology (IEEE)-Vol. 7, Iss: 10, pp 1691-1701
TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.
Abstract: An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.
Citations
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TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).
Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.
45 citations
Cites background or methods from "Efficient Modeling of Power Supply ..."
...modeling of power supply induced jitter (EMPSIJ)] [46] are fundamentally and analytically same in the case of small values of noise....
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...1) Efficient Modeling of Power Supply Induced Jitter: A recently introduced methodology based on the calculation of the slope of the output, named EMPSIJ, is explained in [46]....
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...In [46], the details of the derivation of the above relationship...
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...A function for differential output response of the VM driver (the same circuit as used in [46]) is formulated....
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...18 shows the piecewise nonlinear modeling of the differential output voltage (rising edge) for a VM driver circuit [46]....
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TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.
Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.
30 citations
Cites background or methods from "Efficient Modeling of Power Supply ..."
...3) EMPSIJ method [1] is advanced to handle N -cascaded CMOS inverter stages....
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...Several methods can be found in the literature for jitter estimation [1], [6]–[16]....
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...In this section, development of the proposed jitter estimation algorithm for a chain of inverters using the noise transfer functions derived in Section III and the proposed extension of the EMPSIJ method [1] are presented for handling a chain of inverters....
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...In [1], a semi-analytical method (EMPSIJ) based on separating the large-signal and small-signal analysis, was introduced to efficiently estimate the PSIJ for circuits with voltage-mode drivers....
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...EMPSIJ method [1] for estimation of PSIJ is based on separate analyzes of large-signal and small-signal voltages in a circuit....
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TL;DR: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented and a significant speedup is demonstrated using the proposed approach.
Abstract: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.
13 citations
TL;DR: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach and reports a significant speed-up reported compared with the simulations by a commercial simulator.
Abstract: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach. The methodology is described in detail through an example of a voltage-mode driver circuit. There is a significant speed-up reported compared with the simulations by a commercial simulator.
12 citations
Cites background from "Efficient Modeling of Power Supply ..."
...Small-signal equivalent model for noise transfer from the PDN to the output [7]....
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...Equivalent circuit for modeling rising edges [7]....
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...1 shows the circuit of a voltage-mode driver commonly used in high-speed transmission links for differential-mode operation [7]....
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TL;DR: In this article, an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN) is presented, where the deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition.
Abstract: This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.
11 citations
References
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20 Nov 2014
TL;DR: The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head and the impact is evaluated by supply noise induced jitter modeling.
Abstract: As data rate of serial interface has increased dramatically, timing margin has gotten tighter and tighter. Supply voltage has also kept deducing according to silicon process technology. However, supply noise is hardly reduced due to higher data rate, a huge number of transistors and slower improvement of packaging technology. Therefore, the jitter due to supply noise can be quite large compared to other jitter components. The jitter due to supply noise is not cancelled out by CDR or PLL at the receiver since PDN resonance frequency is higher than loop bandwidth of CDR or PLL. It is not cost effective if only PDN improvement is adopted to reduce supply noise induced jitter. It is essential to optimize performance at architecture level including circuits and PDN. In this paper, the new technique is proposed to minimize supply noise induced jitter in high speed serial interface. The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head. The impact is evaluated by supply noise induced jitter modeling.
19 citations
"Efficient Modeling of Power Supply ..." refers methods in this paper
...[6] focus on equalization technique based on jitter sensitivity and jitter reduction via architectural level changes....
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15 Mar 2015
TL;DR: In this article, the authors present a study of power-supply noise and ground noise impact on the timing properties of short pulse generation circuits and propose a response surface model combined with Latin Hypercube Sampling (LHS) to model the timing jitter.
Abstract: This paper presents a study of power-supply noise and ground noise impact on the timing properties of short pulse generation circuits. The timing jitter of the measured pulses is mainly from the trigger pulse generator in the circuit consisting of conventional CMOS inverters and NAND gates. Furthermore, the response surface model combined with Latin Hypercube Sampling (LHS) is proposed to model the timing jitter of short pulse generation circuits. The analytical model is verified with Cadence using 0.13 µm CMOS technology. In order to reduce the timing jitter, MOS current-mode logic (MCML) circuits are used in the trigger pulse generator. Up to 50% improvement on the timing jitter can be obtained, due to the differential structure of MCML circuits.
15 citations
"Efficient Modeling of Power Supply ..." refers methods in this paper
...[10] present a method for jitter estimation based on experimental design techniques (such as response surface model and Latin Hypercubes)....
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TL;DR: In this article, the enhanced statistical link analysis method considering both intersymbol interference (ISI) and supply voltage fluctuations is clearly reformulated and experimentally validated step by step by various measurements.
Abstract: Statistical link analysis methods were previously developed for effective computation of bit error rate due to intersymbol interference (ISI). In addition to ISI, supply voltage fluctuations at output drivers can cause jitter and amplitude uncertainty in I/O links. In this paper, the enhanced statistical link analysis method considering both ISI and supply voltage fluctuations is clearly reformulated and experimentally validated step by step by various measurements. A silicon integrated circuit (IC) is designed, fabricated, and assembled on a manufactured printed circuit board (PCB). The supply voltage fluctuations on the IC with regard to the receiver reference voltage are extracted from measurements at the IC and PCB. Also, the impulse response of the total output channel is extracted from the measurements of the driver and channel characteristics. The statistical eye diagrams of the channel output including both ISI effects and the supply voltage fluctuations are then calculated and validated by comparison with the direct eye measurements.
15 citations
08 May 2016
TL;DR: In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed, and the analysis can be extended generically for System-On-Chip (SoC) level design considerations.
Abstract: Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.
14 citations
"Efficient Modeling of Power Supply ..." refers background or result in this paper
...2 [12] is a typical scalable low-voltage signaling transmitter driver....
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...In [11] and [12], initial results of analysis of PSIJ based on separating the large signal response and small signal noise output were introduced....
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...In earlier literature, PSIJ is addressed in various papers [4]–[12]....
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TL;DR: In this article, the jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived and compared with the measured jitter histograms.
Abstract: The jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived. For experimental validation, an integrated circuit (IC) is designed, fabricated, and assembled in a printed circuit board (PCB). The on-chip supply voltage fluctuations are extracted from the simultaneous measurements at the pads on IC and PCB and used to calculate the jitter PDF of the multistage buffers. Also, characteristics of the output channels are measured and modeled with the separately designed channel pattern. Finally, the jitter PDFs for multistage buffers are calculated and compared with the measured jitter histograms.
10 citations