Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

doi:10.1109/TCPMT.2017.2711480

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Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

Journal Article•DOI•

Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

Jai Narayan Tripathi¹, Ramachandra Achar², Rakesh Malik¹•Institutions (2)

STMicroelectronics¹, Carleton University²

03 Jul 2017-IEEE Transactions on Components, Packaging and Manufacturing Technology (IEEE)-Vol. 7, Iss: 10, pp 1691-1701

TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.

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Abstract: An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.

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Journal Article•DOI•

A Review on Power Supply Induced Jitter

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Jai Narayan Tripathi¹, Vijender Kumar Sharma², Hitesh Shrimali²•Institutions (2)

STMicroelectronics¹, Indian Institute of Technology Mandi²

01 Mar 2019-IEEE Transactions on Components, Packaging and Manufacturing Technology

TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).

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Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

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45 citations

Cites background or methods from "Efficient Modeling of Power Supply ..."

...modeling of power supply induced jitter (EMPSIJ)] [46] are fundamentally and analytically same in the case of small values of noise....
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...1) Efficient Modeling of Power Supply Induced Jitter: A recently introduced methodology based on the calculation of the slope of the output, named EMPSIJ, is explained in [46]....
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...In [46], the details of the derivation of the above relationship...
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...A function for differential output response of the VM driver (the same circuit as used in [46]) is formulated....
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...18 shows the piecewise nonlinear modeling of the differential output voltage (rising edge) for a VM driver circuit [46]....
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Journal Article•DOI•

Efficient Jitter Analysis for a Chain of CMOS Inverters

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Jai Narayan Tripathi¹, Puneet Arora², Hitesh Shrimali³, Ramachandra Achar⁴•Institutions (4)

STMicroelectronics¹, Synopsys², Indian Institute of Technology Mandi³, Carleton University⁴

01 Feb 2020-IEEE Transactions on Electromagnetic Compatibility

TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.

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Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.

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30 citations

Cites background or methods from "Efficient Modeling of Power Supply ..."

...3) EMPSIJ method [1] is advanced to handle N -cascaded CMOS inverter stages....
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...Several methods can be found in the literature for jitter estimation [1], [6]–[16]....
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...In this section, development of the proposed jitter estimation algorithm for a chain of inverters using the noise transfer functions derived in Section III and the proposed extension of the EMPSIJ method [1] are presented for handling a chain of inverters....
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...In [1], a semi-analytical method (EMPSIJ) based on separating the large-signal and small-signal analysis, was introduced to efficiently estimate the PSIJ for circuits with voltage-mode drivers....
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...EMPSIJ method [1] for estimation of PSIJ is based on separate analyzes of large-signal and small-signal voltages in a circuit....
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Journal Article•DOI•

Fast Analysis of Time Interval Error in Current-Mode Drivers

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Jai Narayan Tripathi¹, Ramachandra Achar², Rakesh Malik¹•Institutions (2)

STMicroelectronics¹, Carleton University²

27 Oct 2017-IEEE Transactions on Very Large Scale Integration Systems

TL;DR: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented and a significant speedup is demonstrated using the proposed approach.

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Abstract: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.

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13 citations

Journal Article•DOI•

An Efficient Estimation of Power Supply-Induced Jitter by Numerical Method

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Jai Narayan Tripathi¹, Flavio Canavero²•Institutions (2)

STMicroelectronics¹, Polytechnic University of Turin²

26 Oct 2017-IEEE Microwave and Wireless Components Letters

TL;DR: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach and reports a significant speed-up reported compared with the simulations by a commercial simulator.

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Abstract: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach. The methodology is described in detail through an example of a voltage-mode driver circuit. There is a significant speed-up reported compared with the simulations by a commercial simulator.

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12 citations

Cites background from "Efficient Modeling of Power Supply ..."

...Small-signal equivalent model for noise transfer from the PDN to the output [7]....
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...Equivalent circuit for modeling rising edges [7]....
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...1 shows the circuit of a voltage-mode driver commonly used in high-speed transmission links for differential-mode operation [7]....
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Journal Article•DOI•

Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters

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Puneet Arora¹, Jai Narayan Tripathi², Hitesh Shrimali¹•Institutions (2)

Indian Institute of Technology Mandi¹, Indian Institute of Technology, Jodhpur²

31 May 2021-IEEE Transactions on Electron Devices

TL;DR: In this article, an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN) is presented, where the deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition.

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Abstract: This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.

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11 citations

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References

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Open Access

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Book•

Bio and nano packaging techniques for electron devices : advances in electronic device packaging

[...]

Gerald Gerlach, Klaus-Jürgen Wolter

01 Jan 2012

TL;DR: In this paper, a 3D modeling and design for Nems is presented, along with a system-in-package system for Mems and Moems for thermal management, including thermal management.

...read moreread less

Abstract: General Aspects.- 3D Modelling and Design for Nems.- Nanoparticles.- Nanopatterning.- Metallization.- Nano- and Bio-Functionalized Surfaces.- Biocompatible Packaging.- Thermal Management.- System-In-Package For Mems and Moems.

...read moreread less

9 citations

"Efficient Modeling of Power Supply ..." refers background in this paper

...Consequently, the emerging design trends with sharper signal edges and reduced voltage/timing margins have posed numerous signal and power integrity challenges [1], [2]....
[...]

Proceedings Article•DOI•

Noise transfer from receiver to transmitter circuits of tranceivers through power supply network(PDN)

[...]

Janani Chandrasekhar¹, Yujeong Shim¹•Institutions (1)

Altera¹

01 Aug 2014

TL;DR: This paper presents a study on noise transfer from receiver to transmitter circuits of high-speed tranceivers through a commonly connected power delivery network (PDN) on package or printed circuit board (PCB).

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Abstract: This paper presents a study on noise transfer from receiver to transmitter circuits of high-speed tranceivers through a commonly connected power delivery network (PDN) on package or printed circuit board (PCB). Receiver circuits like decision-feedback equalizer (DFE) are power hungry and can generate lot of current on the PDN. Jitter and noise measurements are performed to quantify the amount of noise generated in the receiver (RX) PDN and its impact on the transmitter (TX) when RX and TX share their PDN at the package. Power supply noise induced jitter is then simulated and correlated with measurements to evaluate PDN configuration with TX and RX PDN combined on PCB.

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9 citations

"Efficient Modeling of Power Supply ..." refers background in this paper

...Chandrasekhar and Shim [5] discuss noise transfer from a receiver to a transmitter through a common power delivery network (PDN)....
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...Shim et al. [6] focus on equalization technique based on jitter sensitivity and jitter reduction via architectural level changes....
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Proceedings Article•DOI•

Calculation of power-supply-induced jitter at a 3-D IC channel including ESD protection circuits

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Eunkyeong Park¹, Jingook Kim¹, Jong-Joo Lee², Youngwoo Park²•Institutions (2)

Ulsan National Institute of Science and Technology¹, Samsung²

01 Aug 2015

TL;DR: In this article, the step response of a single-ended output driver with silicon interposer channel is derived including the parasitics of ESD protection circuits, and the probability density functions of the output voltage due to supply voltage fluctuations are also analytically calculated.

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Abstract: The step response of a single ended output driver with silicon interposer channel is derived including the parasitics of ESD protection circuits. The probability density functions of the output voltage due to supply voltage fluctuations are also analytically calculated. With changing the frequency of supply voltage fluctuations, the effect of ESD parasitics on the output jitter is calculated and compared.

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8 citations

"Efficient Modeling of Power Supply ..." refers background in this paper

...[9] take into account the effect of a silicon interposer channel and parasitics of an ESD protection circuit on the output noise response....
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Proceedings Article•DOI•

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

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Hai Lan¹, Minghui Han¹, R. Schmitt¹•Institutions (1)

Rambus¹

01 Oct 2012

TL;DR: The power supply noise induced jitter is derived by combining the noise spectrum and sensitivity profile and the final PSIJ prediction matches closely with the on-chip measurement result.

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Abstract: Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ prediction matches closely with the on-chip measurement result.

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8 citations

Additional excerpts

...PSIJ analysis via jitter sensitivity function can be found in [4]–[8]....
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Proceedings Article•DOI•

Analysis of a serial link for power supply induced jitter

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Jai Narayan Tripathi¹, Hiten Advani², Raj Kumar Nagpal², Vijender Kumar Sharma³, Rakesh Malik¹ - Show less +1 more•Institutions (3)

STMicroelectronics¹, Synopsys², Indraprastha Institute of Information Technology³

01 Sep 2015

TL;DR: An analysis of power supply induced jitter in a high speed serial link using a small signal equivalent model which can be used generically for System-On-Chip (SoC) level design considerations.

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Abstract: An analysis of power supply induced jitter in a high speed serial link is presented in this paper. An equivalent reduced model for serial link is used for the analysis. Jitter induced by the ripples in power delivery network is analyzed by a small signal equivalent model. The effect is modeled by a transfer function which is not technology specific and can be used generically for System-On-Chip (SoC) level design considerations. The analysis is supported by experimental results by simulation in 130nm BiCMoS RF technology and 28nm FDSOI technology (both technologies are of STMicroelectronics).

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5 citations

"Efficient Modeling of Power Supply ..." refers result in this paper

...In [11] and [12], initial results of analysis of PSIJ based on separating the large signal response and small signal noise output were introduced....
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