256 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
Electrical Modeling and Characterization of Through
Silicon via for Three-Dimensional ICs
Guruprasad Katti, Michele Stucchi, Kristin De Meyer, and Wim Dehaene, Senior Member, IEEE
Abstract—Three-dimensional ICs provide a promising option to
build high-performance compact SoCs by stacking one or more
chips vertically. Through silicon vias (TSVs) form an integral
component of the 3-D IC technology by enabling vertical intercon-
nections in 3-D ICs. TSV resistance, inductance, and capacitance
need to be modeled to determine their impact on the performance
of a 3-D circuit. In this paper, the RLC parameters of the TSV are
modeled as a function of physical parameters and material charac-
teristics. Models are validated with the numerical simulators like
Raphael and Sdevice and with experimental measurements. The
TSV RLC model is applied to predict the resistance, inductance,
and capacitances of small-geometry TSV architectures. Finally,
this paper also proposes a simplified lumped TSV model that can
be used to simulate 3-D circuits.
Index Terms—Three-dimensional ICs, through silicon via
(TSV), TSV lumped RLC model.
I. INTRODUCTION
B
ENEFITS of 3-D integrated circuits (ICs) include im-
proved packing density, better noise immunity, reduced
power consumption, and faster speed due to reduced wire
length/lower wire capacitance. In addition, 3-D ICs are promis-
ing for the heterogeneous integration of different technologies
(logic, memory, RF, analog, etc.) which would enable high-
performance and compact SoCs [1]. The fabrication of 3-D
stacked IC (SIC) involves stacking of one or more chips, and
the through silicon via (TSV) [2] constitutes a key component
for interconnecting chips vertically and forms a cylindrical
metal–oxide–semiconductor (MOS) capacitor with the semi-
conductor substrate acting as the bulk and the TSV metal acting
as a gate.
The impact of TSV on the 3-D circuit performance needs
to be evaluated, and there have been attempts to characterize
the resistance and capacitance of TSV [3], [4]. The microwave
characterization of TSV [5] and the extraction of the high-
frequency electrical circuit model of TSV based on S-parameter
measurements [6] have been attempted. Cheng et al. [3] have
presented the TSV C–V characteristics but do not attempt
to model the TSV. The TSV structure in [3] also involves
Manuscript received June 16, 2009; revised September 28, 2009. First
published November 24, 2009; current version published December 23, 2009.
The review of this paper was arranged by Editor J. Woo.
G. Katti, K. De Meyer, and W. Dehaene are with IMEC, 3001 Leuven,
Belgium, and also with the Department of Electrical Engineering, Katholieke
Universiteit Leuven, Leuven 3001, Belgium (e-mail: guruprasad.katti@
imec.be).
M. Stucchi is with IMEC, Leuven 3001, Belgium.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2009.2034508
Fig. 1. TSV architecture.
a predominant reversed bias capacitance of the p-n junction
diodes. Moreover, the TSV structure and the 3-D process used
in [3] and [4] are different when compared to the TSV process
[7] adopted today. Leung and Chen [5] measured the resistance
and inductance of large TSV structures but do not correlate
them with the physical dimensions and material characteristics.
Ryu et al. [6] extract the resistance, inductance, and capacitance
of the TSV from S-parameter measurements but the corela-
tion to the physical dimensions and material properties of the
TSV is missing. In this paper, the TSV resistance (R
TSV
),
inductance (L
TSV
), and capacitance (C
TSV
) are modeled as
a function of physical dimensions and material characteristics
of the TSV. A validated lumped TSV model built using the
TSV RLC parameters is then approximated to form a simple
lumped TSV model, which enables fast yet accurate 3-D circuit
simulations.
First-order expressions for R
TSV
, L
TSV
, and C
TSV
as a
function of physical parameters and material characteristics are
derived and validated with numerical simulators like Raphael
[8] and Sdevice [9] in Section II. Electrical measurements per-
formed to characterize R
TSV
, L
TSV
, and C
TSV
further validate
the models in Section III. Validated models are then extended
to predict the RLC parameters of the future small-geometry
TSV structures foreseen in ITRS [10]. A lumped model for the
TSV using R
TSV
, L
TSV
, and C
TSV
is proposed and further
simplified in Section IV. Section V concludes this paper.
II. R
TSV
, L
TSV
, AND C
TSV
MODELING
In the 3-D TSV first approach [7], TSVs are fabricated after
FEOL processing and before BEOL processing and enable the
interconnection between the Top Metal of the bottom tier and
Metal1 of the top tier, as shown in the cross section of Fig. 1.
Analytical modeling starting from the basic electrodynamic
principles aid in understanding the impact of physical and
technological parameters on R
TSV
, L
TSV
, and C
TSV
.
0018-9383/$26.00 © 2009 IEEE
KATTI et al.: ELECTRICAL MODELING AND CHARACTERIZATION OF THROUGH SILICON VIA FOR THREE-DIMENSIONAL ICs 257
TAB LE I
R
TSV_DC
COMPARISON BETWEEN ANALYTICAL MODEL AND RAPHAEL SIMULATIONS
TAB LE II
EMPIRICAL L
TSV
ESTIMATIONS
R
TSV
Model: The analytical expression of the dc resistance
of the TSV is given by
R
TSV_DC
=
ρl
TSV
πr
2
TSV
(1)
where ρ is the resistivity of the conducting material. r
TSV
and
l
TSV
represent the radius and length of the TSV, respectively.
The analytical model and Raphael [8] simulations show very
good agreement for different TSV architectures, as shown
Table I.
For high-frequency signals, however, the increase in resis-
tance due to skin effect should be accounted. Expressions
derived by Goldfarb and Pucel [11] are used to derive the
R
TSV_AC
for higher frequencies. With Cu as TSV conductor,
the resistivity is 16.8 nΩ · m and the frequency where skin depth
is equal to the radius of the TSV is estimated to be 738 MHz for
a TSV with 5-μm diameter and 100-nm oxide liner thickness
and 4.71 GHz for TSV with 2-μm diameter with 50-nm oxide
liner thickness, respectively. As expected, resistance increase
due to skin effect is quite significant for higher diameter TSV
structures.
L
TSV
Model: The partial self-inductance of the TSV de-
pends upon the diameter and length of the TSV and is given
by the following empirical expression [12]:
L
TSV
=
μ
o
4π
⎡
⎢
⎢
⎣
2l
TSV
ln
2
l
TSV
+
r
2
TSV
+
(
2
l
TSV
)
2
r
TSV
+
r
TSV
−
r
2
TSV
+(2l
TSV
)
2
⎤
⎥
⎥
⎦
(2)
where μ
o
is the permeability of free space given by 4π ×
10
−7
H/m. Empirical partial self-inductance model estimation
results are shown in Table II.
For contemporary TSV architectures with 5-μm diameter and
20-μm length, L
TSV
is estimated to be 10 pH. Inductive voltage
drop ωL
TSV
exceeds R
TSV
only for frequencies above 3 GHz,
suggesting that inductance can be ignored for clock frequencies
with rise and fall times below 3 GHz.
C
TSV
Model: An analytical expression for C
TSV
can be
obtained by solving Poisson’s equation. While the planar MOS
capacitor structure has been studied analytically by solving
Poisson’s equation [13] in a Cartesian coordinate system, the
TSV MOS capacitor requires a solution of Poisson’s equation
in a cylindrical coordinate system. It is sufficient to solve a
1-D Poisson’s equation in the radial direction, as the peripheral
(Φ) and the longitudinal (z) variation in potential (Ψ) is
insignificant. The 1-D Poisson’s equation in cylindrical coor-
dinate system with a p-Si substrate is given by
1
r
∂
∂r
r
∂ψ
∂r
=
qN
a
ε
si
(3)
where q is the electron charge, N
a
is the doping concentration
of p-Si substrate, and ε
si
is the permittivity of silicon. The
boundary conditions given by the following equations suggest
that the potential and the electric field (E) at the depletion
radius (R
dep
) shown in the top view of Fig. 1 is zero
ψ|
R
dep
= 0(4)
E|
R
dep
=
∂ψ
∂r
R
dep
= 0. (5)
This is called the partial depletion approximation that consid-
ers a depleted silicon film between R
ox
<r<R
dep
near the
Si−SiO
2
interface while a neutral region for r ≥ R
dep
in p-Si
substrate, as shown in the top view of Fig. 1.
An expression for the potential variation with respect to the
TSV gate voltage based on the solution of Poisson’s equation
and the derivation of the key MOS capacitor parameters, such as
accumulation, depletion, and minimum depletion capacitance
of the TSV, is elaborated in the Appendix. The nature of the
TSV C–V characteristics is similar to the planar MOS capacitor
such that the accumulation capacitance is the oxide capacitance
given as
C
TSVACC
= C
ox
=
2πε
ox
l
TSV
ln
R
ox
R
Metal
. (6)
As the TSV gate bias increases, the depletion capacitance acts
in series with the oxide capacitance such that the effective
capacitance is the series combination of the oxide and de-
pletion capacitances. The minimum depletion capacitance is
258 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
TABLE III
C
TSV
COMPARISON BETWEEN ANALYTICAL MODEL AND RAPHAEL SIMULATIONS
reached when the depletion radius reaches its maximum and is
given by
C
TSVMIN
=
C
ox
C
dep min
C
ox
+ C
dep min
where
C
dep min
=
2πε
si
l
TSV
ln
R
max
R
ox
. (7)
The accumulation and depletion capacitance expressions show
that the C
TSV
is directly proportional to the length of the TSV
and inversely proportional to the TSV dielectric thickness, as
expected. Moreover, R
max
is inversely proportional to substrate
doping concentration such that the depletion capacitance and
threshold voltage would be higher for higher doping concentra-
tion when compared to lower doping concentration. Thus, low-
doped p-Si substrates are an ideal choice to achieve minimum
C
TSV
.
The comparison between Sdevice [9] simulations and the
analytical model results for various TSV parameters is detailed
in Table III. The analytical model is able to accurately pre-
dict the oxide capacitance and minimum depletion capacitance
for varying TSV diameter, oxide liner thickness, and doping
concentration.
R
TSV
and C
TSV
measurement results are shown in the next
section. Experimental results are used to validate the RLC TSV
models. RLC TSV models are further extended to predict the
resistance, inductance, and capacitance values of future small-
geometry TSVs.
III. TSV E
LECTRICAL CHARACTERIZATION
AND
PROGNOSTICS
R
TSV
is characterized from the resistance measurement of
TSV daisy chains, as shown in Fig. 2(a). Fig. 2(b) shows a sin-
gular section of the simulated TSV daisy chain in Raphael [8].
The TSV diameter is 5 μm with 10-μm pitch while TSV length
is reduced to 20 μm after wafer thinning. Raphael simulations
are performed, assuming Cu resistivity to be 16.8 nΩ · m.
Simulated resistance values are in good agreement with the
measurements as shown in Table IV, suggesting the method-
ology can indeed be used to model the resistance of a single
TSV as in Section II.
The L
TSV
empirical model is validated with the inductance
measurements performed by Leung and Chen [5] shown in
Table V. It can be seen that the inductance estimations match
Fig. 2. (a) SEM of 3D-SIC TSV daisy chain after etching away top substrate.
(b) Section of a TSV daisy chain used for Raphael simulations.
with the inductance measurements, and the model can be used
to predict the inductance of future small-geometry TSVs.
C
TSV
is characterized by using the TSV embedded and de-
embedded structures to eliminate the effect of BEOL parasitic
capacitances. Fig. 3(a) shows the TSV cross section, indicating
the resultant effective oxide liner thickness on the top and
bottom of TSV. TSV Sdevice [9] simulation results consider-
ing ε
ox
= 3.9, φ
m
= 4.7 eV, N
a
= 2 × 10
15
/cm
3
, and t
ox
=
118.20 nm with varying fixed oxide charges were compared
with the TSV high-frequency C–V measurements, as shown
in Fig. 3(b). In the desired operating voltage region from 0 to
V
dd
(∼1 V), the TSV exhibits minimum depletion capacitance.
The accumulation and the minimum depletion capacitance
match well with the measurements. Five-percent discrepancy in
the oxide capacitance can be attributed to the reduction of oxide
thickness at the bottom of the tapering TSV. In addition, the
discrepancy in different C–V slopes in the depletion region can
be attributed to the presence of interface states at the Si−SiO
2
interface, which have been ignored during Sdevice simulations.
The ITRS [10] predicts TSV architectures with a diameter
of 1 μm and minimum TSV length of 10 μm by 2015. Figs. 4
and 5 show C
ox
and C
TSVMIN
, respectively, as a function of
TSV diameter and oxide thicknesses with N
a
= 2 × 10
15
/cm
3
and l
TSV
= 20 μm. It can be seen that C
ox
and C
TSVMIN
increase with decreasing oxide liner thickness and increasing
TSV diameter as expected. Shorter TSV length offers lower
C
TSV
, and hence, a thin wafer obtained after grinding and CMP
would offer minimum capacitance compared with a thick wafer.
However, processing a thin wafer increases the processing steps
as the wafer has to undergo bonding and debonding with a
carrier wafer during the 3-D IC fabrication.
The reduction in capacitance by the depletion capacitance
for varying TSV oxide thickness is shown in Fig. 6. The most
KATTI et al.: ELECTRICAL MODELING AND CHARACTERIZATION OF THROUGH SILICON VIA FOR THREE-DIMENSIONAL ICs 259
TAB LE IV
R
APHAEL SIMULATION AND R
TSV
MEASUREMENT COMPARISON
TAB LE V
L
TSV
EMPIRICAL MODEL AND MEASUREMENT COMPARISON
Fig. 3. (a) Single TSV FIB image. (b). Sdevice TSV C–V simulations versus
measurements.
Fig. 4. C
ox
(in femtofarads) variation with TSV diameter and oxide
thickness.
effective reduction is achieved for lower oxide thicknesses. In
fact, for lower oxide thickness, the oxide capacitance becomes
larger and less significant in the series with the depletion
capacitance. The variation of C
TSV
with doping concentration
is shown in Fig. 7. As expected, lower doping concentrations in-
Fig. 5. C
TSVMIN
(in femtofarads) variation with TSV diameter and oxide
thickness.
Fig. 6. C
TSVMIN
reduction for varying TSV oxide thicknesses.
crease the depletion width and hence reduce C
TSVMIN
, making
highly resistive substrate attractive for low-capacitance TSVs.
IV. L
UMPED TSV MODEL
A lumped RLC model for the TSV is shown in Fig. 8(a).
R
TSV
and L
TSV
cause the voltage drop along the intercon-
nected nodes between Metal1 of the top tier and Top Metal of
the bottom tier. C
TSV
is connected between TSV and ground.
As suggested in Section II, for the current TSV dimensions of
5-μm diameter and 20-μm length, L
TSV
is predominant only
for clock frequencies with rise and fall times above 3 GHz
when ωL
TSV
≥ R
TSV
. The approximate model by ignoring
260 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
Fig. 7. C
TSVMIN
variation with doping.
Fig. 8. (a) RLC TSV model. (b) RC TSV model. (c) C TSV model.
Fig. 9. (a) Bottom inverter–TSV–top inverter schematic. (b) Equivalent elec-
trical circuit.
the inductance reduces to a simplified RC model shown in
Fig. 8(b). The impact of R
TSV
and C
TSV
on the TSV delay
can be analyzed with the help of the circuit shown in Fig. 9(a).
The circuit consists of an inverter placed on the bottom tier
driving an inverter on the top tier through TSV and BEOL RC
loads. RC elements appearing in the signal path are shown in
Fig. 9(b). C
ext
and C
int
indicate the output and input capac-
itances of the inverter. R
w_B
and C
w_B
denote the lumped
BEOL load on the bottom tier while R
w_T
and C
w_T
denote
the lumped BEOL load on the top tier.
The following Elmore delay expression is used to analyze the
impact of R
TSV
and C
TSV
on the path delay:
tp = 0.69R
dr
C
ext
+ 0.69(R
dr
+ R
w_B
)C
w_B
+ 0.69(R
dr
+ R
w_B
+ 0.5R
TSV
)C
TSV
+ 0.69(R
dr
+ R
w_B
+ R
TSV
+ R
w_T
)(C
w_T
+ C
int
)
(8)
where R
dr
is the driving resistance of the inverter.
First-hand calculations [14] indicate that C
int
and C
ext
are
on the order of ∼3 fF and the driving resistance of the inverter
is on the order of kiloohms for 0.25-μm technology. Since
C
TSV
= 35 fF is much larger than the C
int
and C
ext
values,
the term (R
dr
+ R
w_B
+ 0.5 R
TSV
)C
TSV
has a larger weight
Fig. 10. RO delay (in microseconds) with varying R
TSV
and C
TSV
.
in determining the delay in (8). Moreover, in (8), the term R
TSV
is always added to the driving resistance of the inverter R
dr
and
BEOL resistances R
w_B
and R
w_T
. Smaller cross sections and
longer lengths of BEOL metal lines provide larger resistances
than estimated R
TSV
= 18 mΩ in contemporary TSV architec-
ture with 5-μm TSV diameter. Hence, R
TSV
would cause a
minimal impact on the delay. A predominant impact of C
TSV
and a reduced impact of R
TSV
approximate the lumped TSV
model, as shown in Fig. 8(c).
To corroborate the aforementioned analysis, a 41-stage ring
oscillator (RO) with inverters in alternate tiers connected by
TSVs is simulated using Spectre [15]. The RO is cascaded with
an eight-stage frequency divider circuit at the output. R
TSV
and
C
TSV
are varied, and their impact on the RO delay is shown in
Fig. 10. Variations in R
TSV
values for a given value of C
TSV
do
not change the RO delay significantly but RO delay increases
significantly with increasing C
TSV
. Thus, changes in R
TSV
show minimal impact on the delay, while the impact of C
TSV
is not negligible. The dynamic power dissipation C
TSV
V
2
dd
f is
also reduced by lower TSV capacitance, and therefore, efforts
should be made to reduce the TSV capacitance.
V. S
UMMARY AND CONCLUSION
The resistance, inductance, and capacitance of a TSV are
modeled as a function of physical parameters and material
characteristics. Estimations of R, L, and C matchverywell
with the numerical simulation results from Raphael and Sdevice
and with experimental measurements. The impact of various
technology parameters on the resistance, inductance, and ca-
pacitance of TSV has been analyzed, and the models are applied
to predict the resistance, inductance, and capacitance of the
small-geometry TSVs. The TSV lumped impedance model
is based on these RLC elements and shows that the TSV
capacitance has the most dominant impact on the delay.
A
PPENDIX
By solving (3) with the boundary conditions given in (4)–(5),
the solution of the potential is derived as
ψ(r)=
qN
a
r
2
4ε
si
−
qN
a
R
2
dep
2ε
si
ln(r)+
qN
a
R
2
dep
4ε
si
(2 ln(R
dep
)−1) .
(A1)