Electroless Nickel Plating for Making Ohmic Contacts to Silicon
01 Apr 1957-Journal of The Electrochemical Society (The Electrochemical Society)-Vol. 104, Iss: 4, pp 226-230
About: This article is published in Journal of The Electrochemical Society.The article was published on 1957-04-01. It has received 145 citations till now. The article focuses on the topics: Electroless nickel plating & Ohmic contact.
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TL;DR: In this article, the development of electroless Ni-P bath, advantages and mechanisms of deposition, and applications of the NiP deposits are discussed, and a comparison of the properties of NiP and Ni-B as well as the recent developments in Ni-phosphorous research are presented.
Abstract: Literature on electroless Ni-P deposition, in recent decades, has dwelled primarily on surface engineering and corrosion-resistant applications. By contrast, we have many research articles devoted to the engineering aspects of the electroless Ni-P depositions and their technology. The present article deals with the development of electroless Ni-P bath, advantages and mechanisms of deposition, and applications of the Ni-P deposits. We also present a comparison of the properties of electroless Ni-P and Ni-B as well as the recent developments in nickel-phosphorous research. We attempt to review these in a detailed manner. We also briefly discuss the future developments of electroless Ni-P.
307 citations
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01 Jan 1984
TL;DR: In this paper, a liquid partially fills an array of micron-wide repentant capillaries in the heat sink substrate, so that surface tension holds the polished back of an IC in intimate thermal contact with the sink.
Abstract: : The design of high-speed integrated circuits and systems is often constrained by thermal considerations. As late as 1981 it was authoritatively predicted that the maximum achievable power flux for liquid-cooled, densely-packed integrated circuits (ICs) would be about 20 W/sq cm. Convective heat-transfer theory indicates that well over 1000 W/sq cm can be compactly removed from ICs at normal operating temperatures, provided microscopic (e.g., 50-microns wide) extended-surface structures are used. The difficulty of constructing high-conductance, low-stress thermal interfaces between ICs and heat sinks suggests the use of an integral heat sink. Accordingly, IC microfabrication techniques were employed to design, fabricate, and test novel, ultracompact water-cooled, laminar-flow, optimized plate-fin and pin-fin heat sinks directly within standard-thickness silicon substrates. Worst-case thermal resistances as low as 0.083 deg C/W were measured from 1-sq cm thin-film resistors (e.g., a 108 deg C temperature rise at 1309 W), in good agreement with predictions. Further increases in heat transfer are achievable. The use of integral liquid-cooled heat sinks in multichip systems presents potential yield, reliability, cost and packaging problems. Attachment of unmodified ICs to micro-heat sinks seems a more attractive approach. A novel die-attachment technique has been developed which avoids the problems of conventional attachments. In this technique, a liquid partially fills an array of micron-wide repentant capillaries in the heat sink substrate, so that surface tension holds the polished back of an IC in intimate thermal contact with the heat sink. The bond is void-free, virtually stress-free, long-lived, and allows repeated detachment and replacement of ICs without damaging the heat sink substrate. The repentant grooves were fabricated by a novel process using electroless plating of nickel onto vertical silicon microgrooves.
217 citations
Cites background from "Electroless Nickel Plating for Maki..."
...Heavily-doped n-type silicon provides a more favorable surface for adhesion, and heat-treated electroless nickel has been used in the past to make ohmic contacts [106]....
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TL;DR: In this paper, the current transport mechanism in an MIS-tunnel diode has been studied by considering both the process of tunneling and the effect of pinholes in the insulating layer.
Abstract: The current transport mechanism in an MIS-tunnel diode has been studied by considering both the process of tunneling and the effect of pinholes in the insulating layer. It has been shown that in order to explain the experimental J - V characteristics of MIS-diodes, presence of a thin interfacial layer of thickness δ p within the pinholes should be considered. From an analysis of the tJ - V and C - V characteristics, a method has been suggested for the estimation of the value of δ p . The values of interface trap density and barrier height for the MOS-part of the diodes are also calculated. The dependence of barrier height on oxide thickness for the diodes is found to obey the barrier height model of Cowley and Sze.
187 citations
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IBM1
TL;DR: In this paper, a method for layer transfer of a base layer from a wafer of a III-V substrate, the base layer being less than about 20 microns thick, is presented.
Abstract: A method for forming a heterojunction III-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a III-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer. A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.
92 citations
TL;DR: In this article, a hole trap at Ev+0.48 eV was observed, with an electron trap at Ec-0.28 eV present in the Au-doped material.
Abstract: Deep level defects produced by quenching from 1175 degrees C silicon doped with Au, Ag, Fe, Cu or Ni have been observed using transient capacitance spectroscopy. In both Au- and Ag-doped samples a hole trap at Ev+0.48 eV was observed, with an electron trap at Ec-0.28 eV present in the Au-doped material. In quenched, Fe-doped samples three hole traps were observed (Ev+0.32 eV, Ev+0.39 eV, Ev+0.40 eV), in agreement with previous measurements. In both Cu- and Ni-doped samples, one hole trap was observed (Ev+0.53 eV for Cu, Ev+0.33 eV for Ni), which was also seen in the as-diffused material. Undoped samples displayed a quenched-in, hole trapping defect at Ev+0.43 eV. All defect states, with the exception of the Ev+0.40 eV Fe-interstitial centre, were neutralised to a depth of about 7 mu m by a 2 h exposure at 200 degrees C to a low-pressure hydrogen plasma. Results are also given for the motion of the Ev+0.40 eV Fe-related centre and the Ec-0.28 eV Au-related centre under the action of the electric field in reverse-biased junction diodes. Using a simplified treatment mobilities at 25 degrees C of 9*10-15 cm2V-1s-1 for the Ev+0.40 eV state, and 2*10-15 cm2V-1s-1 for the Ec-0.28 eV state were estimated.
87 citations