Electrothermal Simulation and Thermal Performance Study of GaN Vertical and Lateral Power Transistors
TL;DR: In this article, the authors present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors and compare their thermal performance.
Abstract: In this paper, we present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) and compare their thermal performance. The models are first validated by comparison with experimental dc characteristics, and then used to study the maximum achievable power density of the device without the peak temperature exceeding a safe operation limit of 150°C (P150°C). It is found that the vertical MOSFETs have the potential to achieve a higher P150°C than the lateral HEMTs, especially for higher breakdown voltages and higher scaling level designs.
Citations
More filters
Nagoya University1, University of Grenoble2, University of Padua3, University of Liverpool4, Hong Kong University of Science and Technology5, Massachusetts Institute of Technology6, HRL Laboratories7, University of Sheffield8, Katholieke Universiteit Leuven9, Fraunhofer Society10, Nagoya Institute of Technology11, University of Notre Dame12, Virginia Tech13, Infineon Technologies14, University of Glasgow15, University of Texas at Austin16, University of Bristol17, National Institute of Advanced Industrial Science and Technology18, Cardiff University19, University of Cambridge20, Zhejiang University21
TL;DR: This collection of GaN technology developments is not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve.
Abstract: Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.
788 citations
Cites background from "Electrothermal Simulation and Therm..."
...Vertical GaN power devices have attracted signiicant attention recently, due to the capability of achieving high breakdown voltage (BV) and current levels without enlarging the chip size, the superior reliability gained by moving the peak electric ield away from the surface into bulk devices, and the easier thermal management than lateral devices [48]....
[...]
TL;DR: In this article, a GaN vertical fin power field effect transistor structure with submicron fin-shaped channels on bulk GaN substrates was reported, and a combined dry/wet etch was used to get smooth fin vertical sidewalls.
Abstract: This letter reports a GaN vertical fin power field-effect-transistor structure with submicron fin-shaped channels on bulk GaN substrates. In this vertical transistor design only n-GaN layers are needed, while no material regrowth or p-GaN layer is required. A combined dry/wet etch was used to get smooth fin vertical sidewalls. The fabricated transistor demonstrated a threshold voltage of 1 V and specific on resistance of 0.36 ${\mathrm {m}}\Omega {\mathrm {cm}}^{2}$ . By proper electric field engineering, 800 V blocking voltage was achieved at a gate bias of 0 V.
198 citations
Cites background from "Electrothermal Simulation and Therm..."
...However for high-voltage high-current applications, a vertical structure is preferred [11] because: 1) its die area does not depend on the breakdown voltage; 2) the surface is far from the high electric field regions, which minimizes trapping effects; 3) high current levels are typically possible thanks to the easier current extraction when the source and drain contacts are positioned vertically in opposite sides of the wafer; and 4) high thermal performance due to a more spread current and electrical field distribution [12]....
[...]
164 citations
TL;DR: In this article, the authors demonstrated GaN vertical Schottky and p-n diodes on Si substrates for the first time, achieving a breakdown voltage of 205 V and a soft BV higher than 300 V, respectively, with peak electric field of 2.9 MV/cm in GaN.
Abstract: This letter demonstrates GaN vertical Schottky and p-n diodes on Si substrates for the first time. With a total GaN drift layer of only 1.5- $\mu{\rm m}$ thick, a breakdown voltage (BV) of 205 V was achieved for GaN-on-Si Schottky diodes, and a soft BV higher than 300 V was achieved for GaN-on-Si p-n diodes with a peak electric field of 2.9 MV/cm in GaN. A trap-assisted space-charge-limited conduction mechanism determined the reverse leakage and breakdown mechanism for GaN-on-Si vertical p-n diodes. The on-resistance was 6 and 10 ${\rm m}\Omega\cdot{\rm cm}^{2}$ for the vertical Schottky and p-n diode, respectively. These results show the promising performance of GaN-on-Si vertical devices for future power applications.
158 citations
Cites background from "Electrothermal Simulation and Therm..."
...GaN vertical devices have attracted increased attention recently, due to their potential for sustaining high breakdown voltage (BV ) without enlarging chip size [2], suitability to have the peak electric field away from the surface [1], and superior thermal performance [2]....
[...]
TL;DR: In this article, an advanced edge termination technology has been developed by combining plasma treatment, tetramethylammonium hydroxide wet etching, and ion implantation to suppress the leakage along the etch sidewall.
Abstract: Conventional GaN vertical devices, though promising for high-power applications, need expensive GaN substrates. Recently, low-cost GaN-on-Si vertical diodes have been demonstrated for the first time. This paper presents a systematic study to understand and control the OFF-state leakage current in the GaN-on-Si vertical diodes. Various leakage sources were investigated and separated, including leakage through the bulk drift region, passivation layer, etch sidewall, and transition layers. To suppress the leakage along the etch sidewall, an advanced edge termination technology has been developed by combining plasma treatment, tetramethylammonium hydroxide wet etching, and ion implantation. With this advanced edge termination technology, an OFF-state leakage current similar to Si, SiC, and GaN lateral devices has been achieved in the GaN-on-Si vertical diodes with over 300 V breakdown voltage and 2.9-MV/cm peak electric field. The origin of the remaining OFF-state leakage current can be explained by a combination of electron tunneling at the p-GaN/drift-layer interface and carrier hopping between dislocation traps. The low leakage current achieved in these devices demonstrates the great potential of the GaN-on-Si vertical device as a new low-cost candidate for high-performance power electronics.
132 citations
Cites background from "Electrothermal Simulation and Therm..."
...GaN vertical devices have attracted increased attention recently, due to several potential advantages over GaN lateral devices: 1) higher breakdown voltage (BV) capability without enlarging chip size [2]; 2) superior reliability due to the peak electric field (Epeak) being far away from the surface; and 3) superior thermal performance [2]....
[...]
References
More filters
20 May 2010
TL;DR: In this article, GaN power transistors on Si substrates for power switching application are reported, and current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate.
Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were examined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance (Ron) and a high breakdown voltage (Vb).
454 citations
01 Jan 2010
TL;DR: A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance and a high breakdown voltage as well as one of the cost-effective solutions.
Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were exam- ined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance ðRonÞ and a high breakdown voltage ðVbÞ.
448 citations
"Electrothermal Simulation and Therm..." refers background in this paper
...I. INTRODUCTION GALLIUM nitride (GaN)-based transistors are excellentcandidates for high-voltage, high-frequency, and highpower applications because of the superior physical properties of GaN compared to Si, SiC, and GaAs [1]....
[...]
...The main obstacle for this comparison is that, though many thermal studies have been reported for lateral AlGaN/GaN HEMTs [2], [8], [13] as well as SiC- and GaAsbased FETs [3], [9], [14], no thermal analyses or models of vertical GaN MOSFETs have been reported to date....
[...]
...Lateral HEMTs have been studied extensively for power devices and have demonstrated a record combination of low on-resistance and high breakdown voltage (Vbr), but still face reliability and integration challenges [1]....
[...]
...GALLIUM nitride (GaN)-based transistors are excellent candidates for high-voltage, high-frequency, and highpower applications because of the superior physical properties of GaN compared to Si, SiC, and GaAs [1]....
[...]
TL;DR: In this paper, the authors report on the noninvasive measurement of temperature, i.e., self-heating effects, in active AlGaN/GaN HFETs grown on sapphire and SiC substrates.
Abstract: We report on the noninvasive measurement of temperature, i.e., self-heating effects, in active AlGaN/GaN HFETs grown on sapphire and SiC substrates. Micro-Raman spectroscopy was used to produce temperature maps with /spl ap/1 /spl mu/m spatial resolution and a temperature accuracy of better than 10/spl deg/C. Significant temperature rises up to 180/spl deg/C were measured in the device gate-drain opening. Results from a three-dimensional (3-D) heat dissipation model are in reasonably good agreement with the experimental data. Comparison of devices fabricated on sapphire and SiC substrates indicated that the SiC substrate devices had /spl sim/5 times lower thermal resistance.
342 citations
Additional excerpts
...2261072 pure thermal models [2], [6], [7]....
[...]
TL;DR: In this paper, the heat transport mechanisms in superlattices are identified from the cross-plane thermal conductivity Λ of (AlN)x-(GaN)y super-attices measured by time-domain thermoreflectance, attributed to differences in the roughness of the AlN/GaN interfaces.
Abstract: The heat transport mechanisms in superlattices are identified from the cross-plane thermal conductivity Λ of (AlN)x–(GaN)y superlattices measured by time-domain thermoreflectance. For (AlN)4.1 nm–(GaN)55 nm superlattices grown under different conditions, Λ varies by a factor of two; this is attributed to differences in the roughness of the AlN/GaN interfaces. Under the growth condition that gives the lowest Λ, Λ of (AlN)4 nm–(GaN)y superlattices decreases monotonically as y decreases, Λ = 6.35 W m−1 K−1 at y = 2.2 nm, 35 times smaller than Λ of bulk GaN. For long-period superlattices (y > 40 nm), the mean thermal conductance G of AlN/GaN interfaces is independent of y, G ≈ 620 MW m−2 K−1. For y < 40 nm, the apparent value of G increases with decreasing y, reaching G ≈ 2 GW m−2 K−1 at y < 3 nm. MeV ion bombardment is used to help determine which phonons are responsible for heat transport in short period superlattices. The thermal conductivity of an (AlN)4.1 nm–(GaN)4.9 nm superlattice irradiated by 2.3 MeV Ar ions to a dose of 2 × 1014 ions cm−2 is reduced by <35%, suggesting that heat transport in these short-period superlattices is dominated by long-wavelength acoustic phonons. Calculations using a Debye-Callaway model and the assumption of a boundary scattering rate that varies with phonon-wavelength successfully capture the temperature, period, and ion-dose dependence of Λ.
206 citations
TL;DR: In this article, the authors achieved a 9?m-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density (DD).
Abstract: We have achieved a 9 ?m-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density (DD). The crack-free 9 ?m-thick epilayer included 2 ?m i-GaN and 7 ?m buffer. The HEMTs fabricated on these devices showed a maximum drain-current density of 625 mA/mm, transconductance of 190 mS/mm, and a high three-terminal OFF breakdown of 403 V for device dimensions of LgWgLgd=1.5/15/3 ?m . Without using a gate field plate, this is the highest BV reported on an AlGaN/GaN HEMT on silicon for a short Lgd of 3 ?m. A very high BV of 1813 V across 10 ?m ohmic gap was achieved for i-GaN grown on thick buffers. As the thickness of buffer layers increased, the decreased DD of GaN and increased resistance between surface electrode and substrate yielded a high breakdown.
203 citations
"Electrothermal Simulation and Therm..." refers result in this paper
...This relationship and value of the slope are consistent with other reports [20], [21]....
[...]
...Similar structures have been reported in many publications [20], [21]....
[...]