Proceedings ArticleDOI
Enabling architectural innovations using non-volatile memory
Vijaykrishnan Narayanan,Vinay Saripalli,Karthik Swaminathan,Ravindhiran Mukundrajan,Guangyu Sun,Yuan Xie,Suman Datta +6 more
- pp 439-444
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TLDR
This work uses the STT-MRAM to create a reliable copy of SRAM structures vulnerable to radiation-induced transient errors to improve reliability, and shows a hybrid cache architecture that uses a mix of emerging TFET technology and STT -MRAM technology.Abstract:
The emergence of non-volatile memory technologies such as Spin Torque Transfer Magneto-resistive Random Access Memory RAM and Phase Change Memories provide new opportunities for architectural innovations. While the zero off-state leakage, fast read access and high densities of these memories make them attractive options as compared to SRAM, their high write energies and latencies as well as their endurance are a concern. We provide three different architectural techniques that utilize the STT-MRAM characteristics to enable new functionalities. First, we show how exploiting the higher density of STT-MRAM in embedded multi-tasked systems can reduce the context switch overhead. Second, we use the STT-MRAM to create a reliable copy of SRAM structures vulnerable to radiation-induced transient errors to improve reliability. Finally, we show a hybrid cache architecture that uses a mix of emerging TFET technology and STT-MRAM technology. Our results indicate that active leakage is still a concern in STT-MRAM structures.read more
Citations
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Journal ArticleDOI
A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems
TL;DR: Experimental results show that Balloon-FTL can effectively improve the performance and lifespan of the TLC/SLC dual-mode flash memory in embedded systems.
Proceedings ArticleDOI
Hybrid CMOS-TFET based register files for energy-efficient GPGPUs
Zhi Li,Jingweijia Tan,Xin Fu +2 more
TL;DR: This study proposes the hybrid CMOS-TFET based register files and shows that the proposed technique achieves 30% energy reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.
Proceedings ArticleDOI
TLC-FTL: Workload-Aware Flash Translation Layer for TLC/SLC Dual-Mode Flash Memory in Embedded Systems
TL;DR: Experimental results show that TLC-FTL can effectively improve the performance and lifetime of the TLC/SLC dual-mode flash memory in embedded systems.
Journal ArticleDOI
Emerging technology enabled energy-efficient GPGPUs register file
TL;DR: This study first design the hybrid CMOS-TFET based register file, and proposes the memory-contention-aware TFET register allocation (MEM_RA), which develops the TFET-register-utilization-aware block allocation (TUBA) andTFET-regsiter-request-aware warp scheduling (TRWS) mechanisms to effectively utilize the limited TFET registers and achieve the maximal energy savings.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Proceedings ArticleDOI
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
Jason Howard,Saurabh Dighe,Yatin Hoskote,Sriram R. Vangal,D. Finan,G. Ruhl,David Jenkins,H. Wilson,Nitin Borkar,Gerhard Schrom,Fabrice Pailet,Shailendra Jain,Tiju Jacob,Satish Yada,Sravan K. Marella,Praveen Salihundam,Vasantha Erraguntla,Michael Konow,Michael Riepen,Guido Droege,Joerg Lindemann,Matthias Gries,Thomas Apel,Kersten Henriss,Tor Lund-Larsen,Sebastian Steibl,Shekhar Borkar,Vivek De,Rob F. Van der Wijngaart,Timothy G. Mattson +29 more
TL;DR: This paper presents a prototype chip that integrates 48 Pentium™ class IA-32 cores on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery to realize a data-center-on-a-die microprocessor architecture.
Proceedings ArticleDOI
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
TL;DR: This paper stacks MRAM-based L2 caches directly atop CMPs and compares it against SRAM counterparts in terms of performance and energy, and proposes two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache.
Proceedings ArticleDOI
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
TL;DR: It is found that a pure STT-RAM cache hierarchy provides the best energy efficiency, though a hybrid design of SRAM-based L1 caches with reduced-retention STt-RAM L2 and L3 caches eliminates performance loss while still reducing the energy-delay product by more than 70%.
Journal ArticleDOI
The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory
TL;DR: This paper will introduce a new nonlithographic method of producing reconfigurable arrays of MQCAs and/or storage bits that can be configured electrically and provide a brief description of magnetoresistiverandom access memory (MRAM), the first mainstream spintronic nonvolatile random access memory and project how far it can go to provide a truly universal memory.