End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs
16 May 2017-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 25, Iss: 9, pp 2498-2511
TL;DR: This paper proposes a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs, and demonstrates that it can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management.
Abstract: Solutions to the integration challenges of a new thermal sensor technology into 3-D integrated circuits (ICs) will be discussed in this paper Our proposed architecture uses bimetallic thin-film thermocouples, which are thermally linked to points of measurement throughout the 3-D stack with dedicated vias These vias will be similar to thermal through-silicon vias (TSVs) in structure, yet different in functionality We propose a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs A fraction of thermal TSV resources is decoupled from their original use and repurposed for the temperature sensing infrastructure Tradeoffs concerning the reduction of the thermal TSV resources are investigated Furthermore, we present an end-to-end system, including the physical realization of the sensor network as well as its analog interface circuitry with the sensor data sampling unit We demonstrate the operation and correctness of this interface with transistor-level simulations Next, through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a peak temperature constraint of 95 °C)
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TL;DR: The fundamental fabrication technologies of 3D integration are introduced, the recent progresses of MEMS and microsystems using 3D Integration and TSV technologies are reviewed, and the conclusions are made and the future trends are discussed.
45 citations
Dissertation•
16 May 2018
TL;DR: In this article, a methode de conception globale for le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit is presented.
Abstract: L'integration tridimensionnels (3D) ont ete couronnes de succes dans les dispositifs traditionnels pour augmenter la densite logique et reduire les distances de mouvement des donnees. Il resout les limites fondamentales de la mise a l'echelle, par ex. retard croissant dans les interconnexions, les couts de developpement et la variabilite. La plupart des peripheriques de memoire livres aujourd'hui comportent une forme d'empilage de puce. Mais en raison des limites de dissipation de puissance des circuits integres, la frequence de fonctionnement du MPU d'aujourd'hui a ete limitee a quelques GHz. Le but de la these est de fournir une methode de conception globale pour le circuit integre 3D dans le domaine electrique, thermique, electrothermique et aussi le bruit. A cette fin, la question de recherche est la suivante: Comment realiser la conception 3D IC, comment gerer VLS 3D IC et comment resoudre les problemes thermiques dans le CI 3D. Dans ce contexte, les methodes de simulation pour le substrat et egalement la connectivite relative (TSV, RDL, Micro strip et circuits integres dans le substrat) sont proposees. Afin de satisfaire la demande de recherche, un 3D-TLE et une impedance de substrat sont programmes dans Matlab, qui peut automatiquement extraire de tous les contacts; impedance, de forme arbitraire et de matiere arbitraire. L'extracteur est compatible a 100% avec le simulateur de cœur SPICE et verifie avec les resultats de mesure et les resultats de simulation FEM. Et comme pour une demo, une frequence de 26 GHz et un filtre RF de bande passante 2GHz sont proposes dans ce travail. Un autre simulateur electrothermique est egalement programme et verifie avec ADS. En tant que solution a la dissipation thermique locale, le caloduc plat est propose comme composant potentiel. Le modele caloduc est verifie avec une simulation FEM. La methode d'analyse du bruit des substrats et les methodes de calcul de electriques et thermo-mecanique KOZ sont egalement presentees.
6 citations
Cites background from "End-to-End Analysis of Integration ..."
...Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 241 [210] D....
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TL;DR: It is shown that in many cases it is better to disable hot portions of the cache rather than apply DTM and slow down the processor, which can improve the performance of DRAM-targeted DTM by 26.1% on average which make 3-D systems more practical for the future high-performance computing.
Abstract: High bandwidth 3-D-stacked dynamic random access memory (DRAM) has been proposed to address the memory wall in modern systems, especially when it is used as a large last-level cache (LLC). However, stacking DRAM directly on top of the processor significantly impedes the efficiency of cooling, potentially causing thermal issues both in the processor and DRAM. Dynamic thermal management (DTM) based on DRAM temperature can be heavily intrusive because the normal working temperature for DRAM is lower than the processor temperature limit. This paper shows that in many cases it is better to disable hot portions of the cache rather than apply DTM and slow down the processor. Three temperature-aware cache management mechanisms are proposed to decrease the performance impact of DTM on 3-D systems. Our experiments show these techniques can improve the performance of DRAM-targeted DTM by 26.1% on average which make 3-D systems more practical for the future high-performance computing.
4 citations
Cites background from "End-to-End Analysis of Integration ..."
...Furthermore, several temperature sensing techniques have been proposed to accurately sense temperature in 3-D ICs with low-cost [44]–[46]....
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TL;DR: In this paper , a high-efficient design method of TSV array for thermal management of 3D integrated system is developed based on the equivalent thermal conductivity (ETC) model and particle swarm optimization algorithm.
Abstract: In this paper, a high-efficient design method of TSV array for thermal management of 3-dimensional (3D) integrated system is developed based on the equivalent thermal conductivity (ETC) model and particle swarm optimization algorithm. Due to the anisotropy of TSV, the ETC model along the vertical direction is established, and the finite element method (FEM) is utilized to validate the accuracy of the ETC model. The relative error of the peak temperature between FEM and ETC model is less than 1.27%, and the average computational time of ETC model is greatly decreased from 261 to 13.3 s. In addition, the TSV array for heat management of 3D integrated system is investigated and designed by the developed method. According to the designed scheme, the peak and average temperatures of the FEM based on 6×6 TSV array are 314.60 and 303.84 K, which well agree with the desired indexes (315 and 310 K). The temperature differences of top and bottom surfaces are all less than 4.3 K, which implies that the thermal distribution of 3D integrated system is homogeneous. Therefore, the developed design method can efficiently design TSV array to achieve relatively low and uniform thermal distribution, and it can be applied in the 3D integrated heat management system.
2 citations
TL;DR: In this paper , a high-efficient design method of through silicon via (TSV) array for thermal management of 3D integrated system is developed based on the equivalent thermal conductivity (ETC) model and the particle swarm optimization algorithm.
Abstract: In this article, a high-efficient design method of through silicon via (TSV) array for thermal management of 3-dimensional (3-D) integrated system is developed based on the equivalent thermal conductivity (ETC) model and the particle swarm optimization algorithm. Due to the anisotropy of TSV, the ETC model along the vertical direction is established, and the finite element method (FEM) is utilized to validate the accuracy of the ETC model. The relative error of the peak temperature between FEM and ETC model is less than 1.27%, and the average computational time of ETC model is greatly decreased from 261 to 13.3 s. In addition, the TSV array for heat management of 3-D integrated system is investigated and designed by the developed method. According to the designed scheme, the peak and average temperatures of the FEM based on $6\times 6$ TSV array are 314.60 and 303.84 K, which will agree with the desired indexes (315 and 310 K). The temperature differences of top and bottom surfaces are all less than 4.3 K, which implies that the thermal distribution of the 3-D integrated system is homogeneous. Therefore, the developed design method can efficiently design TSV array to achieve relatively low and uniform thermal distribution, and it can be applied in the 3-D integrated heat management system.
1 citations
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TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Abstract: Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
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TL;DR: The energy transfer efficiency of this foldable graphene oxide film-based device fabricated by a scalable process is independent of water quantity and can be achieved without optical or thermal supporting systems, therefore significantly improving the scalability and feasibility of this technology toward a complementary portable and personalized water solution.
Abstract: Because it is able to produce desalinated water directly using solar energy with minimum carbon footprint, solar steam generation and desalination is considered one of the most important technologies to address the increasingly pressing global water scarcity. Despite tremendous progress in the past few years, efficient solar steam generation and desalination can only be achieved for rather limited water quantity with the assistance of concentrators and thermal insulation, not feasible for large-scale applications. The fundamental paradox is that the conventional design of direct absorber−bulk water contact ensures efficient energy transfer and water supply but also has intrinsic thermal loss through bulk water. Here, enabled by a confined 2D water path, we report an efficient (80% under one-sun illumination) and effective (four orders salinity decrement) solar desalination device. More strikingly, because of minimized heat loss, high efficiency of solar desalination is independent of the water quantity and can be maintained without thermal insulation of the container. A foldable graphene oxide film, fabricated by a scalable process, serves as efficient solar absorbers (>94%), vapor channels, and thermal insulators. With unique structure designs fabricated by scalable processes and high and stable efficiency achieved under normal solar illumination independent of water quantity without any supporting systems, our device represents a concrete step for solar desalination to emerge as a complementary portable and personalized clean water solution.
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Abstract: There has been strong demand for novel nonvolatile memory technology for low-cost, large-area, and low-power flexible electronics applications. Resistive memories based on metal oxide thin films have been extensively studied for application as next-generation nonvolatile memory devices. However, although the metal oxide based resistive memories have several advantages, such as good scalability, low-power consumption, and fast switching speed, their application to large-area flexible substrates has been limited due to their material characteristics and necessity of a high-temperature fabrication process. As a promising nonvolatile memory technology for large-area flexible applications, we present a graphene oxide based memory that can be easily fabricated using a room temperature spin-casting method on flexible substrates and has reliable memory performance in terms of retention and endurance. The microscopic origin of the bipolar resistive switching behavior was elucidated and is attributed to rupture and...
541 citations
07 Nov 2004
TL;DR: A thermal-driven 3D floorplanning algorithm with CBA representation that can reduce the wirelength by 29% and reduce the maximum on-chip temperature by 56% is proposed.
Abstract: As the technology progresses, interconnect delays have become bottlenecks of chip performance. 3D integrated circuits are proposed as one way to address this problem. However, thermal problem is a critical challenge for 3D IC circuit design. We propose a thermal-driven 3D floorplanning algorithm. Our contributions include: (1) a new 3D floorplan representation, CBA and new interlayer local operations to more efficiently exploit the solution space; (2) an efficient thermal-driven 3D floorplanning algorithm with an integrated compact resistive network thermal model (CBA-T); (3) two fast thermal-driven 3D floorplanning algorithms using two different thermal models with different runtime and quality (CBA-T-Fast and CBA-T-Hybrid). Our experiments show that the proposed 3D floorplan algorithm with CBA representation can reduce the wirelength by 29% compared with a recent published result from (Hsiu et al., 2004). In addition, compared to a nonthermal-driven 3D floorplanning algorithm, the thermal-driven 3D floorplanning algorithm can reduce the maximum on-chip temperature by 56%.
416 citations
"End-to-End Analysis of Integration ..." refers background in this paper
...A large body of work resulted in dynamic thermal management techniques and cooling solutions for 3-D ICs [2]–[13]....
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TL;DR: The overall objective of this survey is to give microprocessor designers a broad perspective on various aspects of designing thermal-aware microprocessors and to guide future thermal management studies.
Abstract: Microprocessor design has recently encountered many constraints such as power, energy, reliability, and temperature. Among these challenging issues, temperature-related issues have become especially important within the past several years. We summarize recent thermal management techniques for microprocessors, focusing on those that affect or rely on the microarchitecture. We categorize thermal management techniques into six main categories: temperature monitoring, microarchitectural techniques, floorplanning, OS/compiler techniques, liquid cooling techniques, and thermal reliability/security. Temperature monitoring, a requirement for Dynamic Thermal Management (DTM), includes temperature estimation and sensor placement techniques for accurate temperature measurement or estimation. Microarchitectural techniques include both static and dynamic thermal management techniques that control hardware structures. Floorplanning covers a range of thermal-aware floorplanning techniques for 2D and 3D microprocessors. OS/compiler techniques include thermal-aware task scheduling and instruction scheduling techniques. Liquid cooling techniques are higher-capacity alternatives to conventional air cooling techniques. Thermal reliability/security issues cover temperature-dependent reliability modeling, Dynamic Reliability Management (DRM), and malicious codes that specifically cause overheating. Temperature-related issues will only become more challenging as process technology continues to evolve and transistor densities scale up faster than power per transistor scales down. The overall objective of this survey is to give microprocessor designers a broad perspective on various aspects of designing thermal-aware microprocessors and to guide future thermal management studies.
201 citations
"End-to-End Analysis of Integration ..." refers background in this paper
...A large body of work resulted in dynamic thermal management techniques and cooling solutions for 3-D ICs [2]–[13]....
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