Proceedings ArticleDOI
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs
Asma Laraba,Haralampos-G. Stratigopoulos,Salvador Mir,Herve Naudet,Christophe Forel +4 more
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TLDR
Some limitations in the existing version of the reduced code linearity test technique for pipeline ADCs are identified and solutions to enhance its accuracy are provided.Abstract:
The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.read more
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Journal ArticleDOI
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique
TL;DR: It is shown that by exploiting some inherent properties in the architecture of pipeline ADCs the authors can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test.
Journal ArticleDOI
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs
Guillaume Renaud,Manuel J. Barragan,Asma Laraba,Haralampos-G. Stratigopoulos,Salvador Mir,Hervé Le-Gall,Herve Naudet +6 more
TL;DR: This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test techniques for ADC static linearity characterization based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain.
Proceedings ArticleDOI
INL systematic reduced-test technique for Pipeline ADCs
TL;DR: This paper presents a procedure to implement a high efficient test of the Integral Non-linearity (INL) of Pipeline ADCs using an extremely reduced set of test input amplitude levels (one order of magnitude lower than the total number of codes in the ADC).
Proceedings ArticleDOI
Reduced code linearity testing of pipeline adcs in the presence of noise
TL;DR: Experimental measurements demonstrate that this reduced code testing technique estimates the static performances with an accuracy equivalent to the standard histogram technique, and only 6 % of the codes need to be considered which represents a very significant test time reduction.
Journal ArticleDOI
Reduced-Code Linearity Testing of Pipeline ADCs
TL;DR: The authors present a selection and mapping technique that is based on digital monitoring that is an attractive low-cost alternative to the standard techniques based on complete histograms.
References
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Book
Data converters
TL;DR: This book is the first graduate-level textbook presenting a comprehensive treatment of Data Converters, and provides comprehensive definition of the parameters used to specify data converter, and covers all the architectures used in Nyquist-rate data converters.
Proceedings ArticleDOI
An on chip ADC test structure
Yun-Che Wen,Kuen-Jong Lee +1 more
TL;DR: A new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented, using a ramp signal generated by an integrator as a test input signal.
Journal ArticleDOI
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs
TL;DR: This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique and shows that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.
Journal ArticleDOI
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction
TL;DR: A transition-code based method that can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method is proposed.
Journal ArticleDOI
High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy
TL;DR: Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLk error of 12-bit ADCs to a plusmn0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs.