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Proceedings Article•DOI•

Enhanced resist and etch CD control by design perturbation

Puneet Gupta, Andrew B. Kahng1, Chul-Hong Park1•
University of California, San Diego1
08 Nov 2005-Vol. 5992, pp 1085-1095
TL;DR: A novel dynamic programming-based technique for etch-dummy correctness (EtchCorr) which can be combine with the SAEDM in detailed placement of standard-cell designs and is validated on industrial testcases with respect to wafer printability, database complexity and device performance.
Abstract: Etch dummy features are used in the mask data preparation flow to reduce critical dimension (CD) skew between resist and etch processes and improve the printability of layouts. However, etch dummy rules conflict with SRAF (Sub-Resolution Assist Feature) insertion because each of the two techniques requires specific spacings of poly-to-assist, assist-to-assist, active-to-etch dummy and dummy-to-dummy. In this work, we first present a novel SRAF-aware etch dummy insertion method ( SAEDM ) which optimizes etch dummy insertion to make the layout more conducive to assist-feature insertion after etch dummy features have been inserted. However, placed standard-cell layouts may not have the ideal whitespace distribution to allow for optimal etch dummy and assist-feature insertions. Since placement of cells can create forbidden pitch violations, the placer must generate assist-correct and etch dummy-correct placements. This can be achieved by intelligent whitespace management in the placer. We describe a novel dynamic programming-based technique for etch-dummy correctness ( EtchCorr ) which can be combine with the SAEDM in detailed placement of standard-cell designs. Our algorithm is validated on industrial testcases with respect to wafer printability, database complexity and device performance.

Summary (2 min read)

Jump to: [1. INTRODUCTION] – [2. LIBRARY MCC (LMCC)] – [2.1. Layout Parameter Extraction] – [2.2. Experimental Setup] – [3. WIRE MCC (WMCC)] – [3.1. FC Saturation] – [3.2. Line-body, End and Corner Models] – [3.3. FC Prediction] and [4. CONCLUSIONS]

1. INTRODUCTION

  • RET such as assist feature insertion and OPC are mandatory post tapeout steps to ensure printability of features in sub-90nm technology nodes.
  • Since the model provides mask cost as a function of layout parameters, library designers can modify device layout to minimize mask cost without running OPC and fracturing repeatedly.
  • Instead, the authors model the response of the OPC algorithm as a function of OPC tolerances and layout parameters.
  • Layout dimensions and geometries of devices in standard cells is different from that of wires.
  • Hence, MCC approach is different for each.

2. LIBRARY MCC (LMCC)

  • Fracture count of a standard cell is a function of OPC tolerances (IT, OT, SSIDE, FRAG) and its layout context.
  • MCC for isolated context can be performed by running OPC followed by fracturing on individual standard cells for different IT, OT, SSIDE and FRAG.
  • Outer tolerance (OT) specifies the maximum tolerable edge movement outside the drawn feature.
  • Fragmentation (FRAG) is one of the parameters that can have a significant impact on fracture count.
  • The authors identify layout parameters that are the source of fracture count variation between any two standard cells for a given tolerance combination.

2.1. Layout Parameter Extraction

  • The authors explore different characteristics of standard cell layouts that are the source of variation in fracture count for a given tolerance combination.
  • The source of fracture count discrepancy is the layout of the cells.
  • The authors only consider the average spacing between poly, defined as the ratio of cell width to the number of poly features.
  • A simple vertical poly has just four vertices.

2.2. Experimental Setup

  • The authors give details of their OPC setup and regression studies.
  • The authors construct OPC recipes to run OPC exhaustively on all 15 cells for all combinations of IT, OT, SSIDE and FRAG given in Table 2.
  • Based on the fracture count data and layout parameter values for 15 cells, the authors perform regression studies to construct FC model using SPLUS7 software.
  • From the plots the authors can observe that PFC is strongly correlated with NP, CW, PVC and PW.
  • From the results the authors observe that around 62% of the cells have less than 5% error between predicted FC and actual FC.

3. WIRE MCC (WMCC)

  • Wire mask cost (WMC) model predicts the FC of wires before running OPC using pre-characterized models and look-up tables.
  • In addition to tolerance optimization, WMC model can be used for guiding wire sizing optimizations to minimize FC.
  • The model captures the three major contexts of a wire such as the line-body (L), line-end (LE) and the line-corner (C) as shown in Figure 7.
  • Using the FC data, the authors construct closed-form expressions and populate LUTs representing the model.
  • Section 3.1 describes FC saturation in detail.

3.1. FC Saturation

  • The geometries of wires in the layout along with context can be very complex.
  • Parameters for the main pattern start with the letter ’M’ and those of the neighbors start with the letter ’N’.
  • The diffraction effects caused by a small neighbor in the vicinity of the main pattern are corrected aggressively by the OPC tool.
  • The OPC treatment of line-ends and corners of a wire pattern is different from that of the line-body.
  • The general trend in saturation points of various parameters are shown in Figure 10 and their values are summarized in Table 4.

3.2. Line-body, End and Corner Models

  • Based on the saturation points for different parameters, the authors construct different configurations of the line-body, line-end and line-corners and run OPC followed by fracturing.
  • To compute the slope of the model, the authors construct the test patterns shown in Figure 12(a) which shows two main lines M1 and M2 of lengths ML1 and ML2 respectively.
  • Table 6 gives the LUTs for line-end for single and double neighbor cases.
  • The presence of wire patterns around the line-end does not change the fragmentation significantly and hence, the authors see a small change in FC with change in neighbor spacing.
  • Hence, the authors construct LUTs with CCL and EPEtol as parameters and use it for predicting FC of line-corners in real layouts.

3.3. FC Prediction

  • To validate the line-body, line-end and line-corner WMC models presented above, the authors analyze a real layout and predict its FC and compare it with real FC after OPC and fracturing.
  • The authors then extract the optical radius (OR) of the OPC model from a line and space test pattern.
  • These FCs are used to compute α and populate LUTs.
  • To predict FC of real layouts, the predictor decomposes wire patterns from real layouts into the three contexts based on FC windows.
  • Table 8 shows the real and predicted FC for metal layer 2 of ALU128 benchmark in the 90nm technology.

4. CONCLUSIONS

  • The authors have presented methodologies for characterizing OPC of standard cells and wire patterns in terms of fracture count.
  • These FC models can be used by designers to choose between different OPC tolerance combinations to minimize mask cost.
  • The placement of standard cells and the type of standard cells surrounding a given cell have significant impact on its FC.
  • The authors are currently working on extending the library MCC approach to include the impact of layout context.
  • Optimizing line-end corner fragmentation parameters can enable further reductions in FC.

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Modeling OPC Complexity for Design for Manufacturability
Puneet Gupta
a
, Andrew B. Kahng
a,b,c
, Sw amy Muddu
c
, Sam Nakagawa
a
and Chul-Hong
Park
c
a
Blaze DFM Inc, Sunnyvale CA, USA 94089
b
CSE Department, UCSD, La Jolla CA, USA 92093
c
ECE Department, UCSD, La Jolla CA, USA 92037
ABSTRACT
Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution
enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive
optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity
and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask
cost is determined by mask write time and mask inspection time, which are directly related to the complexity of
features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying
existing features.
Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in
several recent works
2
,
3
,
4
. The goal of design-aware OPC is to relax OPC tolerances of layout features to
minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing,
design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires.
Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the
design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in
terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a
critical step in linking design and manufacturing.
In this paper, we present a MCC methodology that provides models of fracture count of standard cells and
wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access
to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a
limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the
characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and
mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.
Keywords: OPC, Fracturing, Mask cost, DFM
1. INTRODUCTION
RET such as assist feature insertion and OPC are mandatory post tapeout steps to ensure printability of features
in sub-90nm technology nodes. Doubling of layout data volume every technology node combined with aggressive
RET is driving mask set cost to prohibitive levels. Transferring design intent to OPC process can reduce the
increasing complexity of masks in sub-90nm technology nodes. Design intent-aware OPC applies different levels
of OPC correction to different regions of a design based on their criticality.
There are two approaches for minimizing mask cost using design information. In the first approach, timing
and power analysis are performed on the design to identify all critical paths and their corresponding layout
features. OPC is then performed with tight tolerances on all critical features and with relaxed tolerances on all
non-critical features to minimize mask cost. This approach (e.g., Cote et.al
2
)doesnotmodifythedesignflow
prior to the tapeout. However, relaxing OPC tolerance uniformly on all non-critical features does not lead to
the best possible mask cost reductions. In the second approach, tolerance optimization is performed by choosing
OPC tolerance combination specific to the standard cell or wire pattern by analyzing its impact on mask cost
and design performance simultaneously. Gupta et.al.
3
propose such an approach for minimizing mask cost by
relaxing OPC tolerances on standard cells, subject to meeting timing constraints . In this flow, OPC tolerance
optimization is performed prior to tapeout.
25th Annual BACUS Symposium on Photomask Technology, edited by J. Tracy Weed, Patrick M. Martin,
Proc. of SPIE Vol. 5992, 59921W, (2005) · 0277-786X/05/$15 · doi: 10.1117/12.633416
Proc. of SPIE Vol. 5992 59921W-1
Characterization of mask cost and timing impact of different OPC tolerances is the basic step for a complete
design-aware OPC flow. In this work, we characterize mask cost of standard cells and wires without performing
OPC repeatedly with different tolerances. Based on the statistical analysis of FC of standard cell and wire
patterns, we construct models and lookup tables of mask cost that can be used for OPC tolerance optimization.
For standard cells, we give models of mask cost of polysilicon layer with inner tolerance (IT), outer tolerance
(OT), starting side (SSIDE) and fragmentation edgelength (FRAG) of feature edges in the layout. Design
engineers can perform trade-offs between parametric yield and mask cost using this model. RET engineers can
use the model of mask cost to tune their OPC recipes without running OPC and fracturing. Since the model
provides mask cost as a function of layout parameters, library designers can modify device layout to minimize
mask cost without running OPC and fracturing repeatedly. Further, MCC can be used to drive mask-friendly
layout optimizations that can potentially improve yield.
OPC adjusts edge placement of features in the layout according to tolerance combination within the specified
number of iterations. In addition to tolerance combination, the final fracture count of an OPC’ed layout depends
on the convergence criterion of the OPC algorithm and the edgelength of fragments. Since OPC algorithm is
iterative, modeling edge placement of features and fracture count is very difficult. Instead, we model the response
of the OPC algorithm as a function of OPC tolerances and layout parameters. Layout dimensions and geometries
of devices in standard cells is different from that of wires. Hence, we perform MCC for standard cells and wires
differently.
To build mask cost models, we assume that fracture counts are generated with sign-off OPC recipes and
optical models. Unless otherwise mentioned, fracture count of a standard cell refers to the fracture count of
polysilicon (poly) layer only. In this work, we do not consider assist feature insertion during MCC. This paper
is organized as follows. In Section 2 we present MCC methodology for standard cells. In Section 3 we present
MCC methodology for wires. Layout styles and properties for standard cells are very different from those in
wires. Hence, MCC approach is different for each. Details of experimental setup and results for standard cell
and wire MCC are presented in their respective sections. Section 4 gives a summary of MCC and presents future
directions.
2. LIBRARY MCC (LMCC)
Fracture count of a standard cell is a function of OPC tolerances (IT, OT, SSIDE, FRAG) and its layout context.
In the absence of any layout feature within the optical radius of influence, fracture count depends entirely on
IT, OT, SSIDE and FRAG. We refer to the absence of features within the distance of optical radius as isolated
context. MCC for isolated context can be performed by running OPC followed by fracturing on individual
standard cells for different IT, OT, SSIDE and FRAG. But in the presence of other standard cells, MCC with
IT, OT, SSIDE and FRAG variation is CPU intensive. In real layouts, standard cells exist in many different
layout contexts with other standard cells. Apart from the different types of standard cells surrounding a given
cell, the placement of cells within the optical radius also impacts the fracture count. Running OPC and fracturing
on all possible contexts with different spacing between standard cells is practically infeasible. To characterize
mask cost of standard cells in a real layout context, we first identify different layout parameters that impact
fracture count in the isolated context. In this work, we perform MCC for isolated context only.
Fracture count of poly layer of a standard cell in isolated context varies primarily with IT, OT, SSIDE and
FRAG. Inner tolerance (IT) specifies the maximum tolerable edge movement inside the drawn feature. Outer
tolerance (OT) specifies the maximum tolerable edge movement outside the drawn feature. Starting side (SSIDE)
provides offset distances (inside and outside a drawn edge) that can be used by the OPC tool to converge on
the edge movements faster. Fragmentation (FRAG) is one of the parameters that can have a significant impact
on fracture count. OPC tools fragment a layout feature into segments and perform movement of these segments
to correct the feature. The number of segments and hence the number of edge movements depend on the
granularity of fragmentation. Fracture count of poly is inversely proportional to the fragment edgelength. Fine-
grained fragmentation may result in fine-grained edge movements, that improve image quality. However, fracture
count increases rapidly as maximum fragment edgelength is decreased. Variation of fracture count for different
IT and OT for different fragmentation edgelengths is shown in Figure 1. For any given IT (or OT), we can
observe a decrease in fracture count as the fragment edgelength is increased. In addition to the parameters
Proc. of SPIE Vol. 5992 59921W-2
described above, fracture count also depends on OPC corrections performed at line-ends and corners. To keep
our exploration space limited, we do not vary line-end and corner correction parameters.
2 3 4 5 6 7 8
360
380
400
420
440
460
480
Inner Tolerance (IT)
Fracture Count
Fracture count of standard cell DFFRHQX1
FRAG=200nm
FRAG=100nm
FRAG=50nm
2 3 4 5 6 7 8
360
380
400
420
440
460
480
Outer Tolerance (OT)
Fracture Count
Fracture count of standard cell DFFRHQX1
FRAG=200nm
FRAG=100nm
FRAG=50nm
Figure 1. Fracture count variation with IT and OT for maximum fragment edgelengths of 50nm, 100nm and 200nm.
Figure 2 shows the flow chart for building MCC model for standard cell library. To construct a FC model,
we choose a subset of standard cells from the library and run OPC exhaustively on all combinations of IT, OT,
SSIDE and FRAG. We then perform fracturing on all OPC stream files and collect fracture count data. We
identify layout parameters that are the source of fracture count variation between any two standard cells for
a given tolerance combination. We then perform linear regression to fit the fracture count of standard cells as
a function of layout parameters for each tolerance combination. We then perform linear regression to fit the
coefficients of layout parameters as a function of OPC tolerances.
Subset of
standard
cells in
library
OPC for all
combinations of
IT, OT, SSIDE,
FRAG
Fracturing
(MEBES)
Layout
parameter
extraction
Regression
Studies
Fracture Count
Model
Fracture Count
Data
Figure 2. Flow chart of LMCC methodology.
2.1. Layout Parameter Extraction
In this section, we explore different characteristics of standard cell layouts that are the source of variation in
fracture count for a given tolerance combination. Figure 3 shows poly and active layers of two standard cells.
Proc. of SPIE Vol. 5992 59921W-3
λ 0.193
NA 0.68
σ
1
, σ
2
0.85, 0.57
Defocus -0.135
Illumination Annular
Reference threshold 0.3
Table 1. Optical model parameters.
IT {−2, −4, −6, −8}nm
OT {2, 4, 6, 8}nm
SSIDE {−20, −10, 0, 10, 25}nm
FRAG {50, 100, 200, 500}nm
Table 2. OPC parameters.
The poly fracture counts of these two cells for any given tolerance combination. The source of fracture count
discrepancy is the layout of the cells. From an initial observation, we can notice that the two cells differ in number
of poly features (NP), cell width (CW) and spacing between poly (PS). The actual fracture count depends on
optical interactions between the features, which in turn depends on the distribution of spacing between the
features. Capturing the distribution of spacing between the poly increases the complexity of analysis. In this
work, we only consider the average spacing between poly, defined as the ratio of cell width to the number of poly
features. The parameter NP does not differentiate between a “simple” vertical poly and a “fingered” poly with
parallel devices. To capture the complexity of features, we consider poly perimeter (PW), which is the total
perimeter of poly in the standard cell. To capture the impact of line ends and corners, we consider poly vertex
count (PVC) which is the total number of vertices of all poly features in the standard cell. A simple vertical
poly has just four vertices. If a notch is added to the vertical poly, the vertex count increases to eight, reflecting
the addition of two convex corners and two concave corners.
Active
CW
Poly vertexPoly
Concave corner
Convex corner
Figure 3. Poly and active regions of two standard cells.
2.2. Experimental Setup
In this section, we give details of our OPC setup and regression studies. To build the fracture count model, we
choose 15 of the most frequently used cells from standard cell benchmarks in the 90nm technology. We construct
optical model with the parameters given in Table 1. We construct OPC recipes to run OPC exhaustively on all
15 cells for all combinations of IT, OT, SSIDE and FRAG given in Table 2. We use CalibreOPC
1
to run OPC
and FractureM (MEBES) to compute total fracture count. IT and OT are implemented using epeToleranceTag.
SSIDE is implemented using opcTag -hintOffset and FRAG using maxedgelength parameter in the fragmen-
tation algorithm. Layout parameters outlined in Section 2.1 are extracted by analyzing standard cell GDSII.
Based on the fracture count data and layout parameter values for 15 cells, we perform regression studies
to construct FC model using SPLUS
7
software. Figure 4 shows a pair-wise scatter plot of poly fracture count
(PFC) along with layout parameters. Column 1 of the figure shows the trend in PFC with NP, CW, PS, PVC
Proc. of SPIE Vol. 5992 59921W-4
and PW. From the plots we can observe that PFC is strongly correlated with NP, CW, PVC and PW. Since
PW is strongly correlated with NP, we choose one of these two for regression.
PFC
1
3
5
7
9
11
260
280
300
320
340
360
380
0
5000
10000
15000
20000
25000
30000
0 50 100 150 200
1357911
NP
CW
10002000300040005000
260280300320340360380
PS
PVC
0 20406080100
050001000015000200002500030000
PW
0
50
100
150
200
1000
2000
3000
4000
5000
0
20
40
60
80
100
GW
0
5000
10000
15000
0 50001000015000
Figure 4. Pair-wise scatter plot showing trends between poly fracture count (PFC) and layout parameters and between
different layout parameters.
For each tolerance combination, we run linear regression to fit FC of all 15 cells as a function of layout
parameters. Figure 5 shows the response and the fit for all 15 cells for a single tolerance combination (IT =
-6, OT = 6, SSIDE = 0, FRAG = 50). Average variance of fit for all 80 tolerance combinations is 0.96, which
implies that 96% of FC variation is accounted for using NP, PVC and PW. To test the fidelity of the fit, we
predict FC of 100 cells using the 15-cell model. We compare predicted FC values to actual FC numbers obtained
from OPC and fracturing. Figure 6 shows predicted and actual FC of 100 cells. From the results we observe that
around 62% of the cells have less than 5% error between predicted FC and actual FC. Around 77% of the cells
have less than 10% error. For all the remaining cells, the trend in predicted FC tracks that of actual FC closely.
Even though the predicted FC differs from the actual FC, the trend in FC is useful for performing tolerance
optimization, since the designer needs to be aware of the change in FC rather than the absolute value.
Fitted : PW + PVC + NP
PFC
50 100 150 200
50 100 150 200
Figure 5. Scatter plot showing actual PFC (dots) versus fit (line) based on three variables, NP, PVC and PW.
3. WIRE MCC (WMCC)
Wire mask cost (WMC) model predicts the FC of wires before running OPC using pre-characterized models and
look-up tables. The objectives of WMCC are: (a) to estimate the change of FC due to different OPC tolerances
and (b) to predict total FC of a layout prior to OPC and fracturing. WMC model can be used to guide choice
Proc. of SPIE Vol. 5992 59921W-5
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07 Jun 2004
TL;DR: In this article, the authors present a design flow that evaluates the application of various restricted design rule (RDR) sets in deep submicron ASIC designs in terms of circuit performance and parametric yield.
Abstract: Resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase-shift mask (PSM) technology are deployed in modern processes to increase the fidelity of printed features, especially critical dimensions (CD) in polysilicon. Even given these exotic technologies, there has been momentum towards less flexibility in layout, in order to ensure printability. However, there has not been a systematic study of the performance and manufacturability impact of such a move towards restrictive design rules. In this paper we present a design flow that evaluates the application of various restricted design rule (RDR) sets in deep submicron ASIC designs in terms of circuit performance and parametric yield. Using such a framework, process and design engineers can identify potential solutions to maximize manufacturability by selectively applying RDRs while maintaining chip performance. In this work we focus attention on the device layer which is the most difficult design layer to manufacture. We quantify the performance, manufacturability and mask cost impact of several common design rules. For instance, we find that small increal3es in the minimum allowable poly line end extension beyond active provide high levels of immunity to lithographic defocus conditions. Also, modification of the minimum field poly to diffusion spacing can provide good manufacturability, while a single pitch single orientation design rule can reduce gate 30σ uncertainty. Both of these improve in data volume as well, with little to no performance penalties. Reductions in data volume and worst-case edge placement error are on the order of 20-30% and 30-50% respectively compared to a standard baseline design rule set.

181 citations

Proceedings Article•DOI•
Manufacturing-aware design methodology for assist feature correctness

[...]

Puneet Gupta, Andrew B. Kahng1, Chul-Hong Park1•
University of California, San Diego1
05 May 2005
TL;DR: In this paper, a dynamic programming-based technique for assist-feature correction (AFCorr) is proposed to handle vertical interactions of field polys between adjacent cell rows in the detailed placement of standard-cell designs.
Abstract: Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in subwavelength lithography As focus levels change during manufacturing, CDs at a given "legal" pitch can fail to achieve manufacturing tolerances required for adequate yield Furthermore, adoption of off-axis illumination (OAI) and SRAF techniques to enhance resolution at minimum pitch worsens printability of patterns at other pitches Our previous work [Gupta et al] described a novel dynamic programming-based technique for Assist-Feature Correctness (AFCorr) to account for interactions within a cell row We now extend the AFCorr methodology to handle vertical interactions of field polys between adjacent cell rows in the detailed placement of standard-cell designs Pattern bridge between field poly geometries becomes a major reason for yield degradation even though CD variation of gates determines circuit performance In this paper, AFCorr is validated in all possible horizontal (H-) and vertical (V-) interactions of polysilicon geometries in the layout For benchmark designs, forbidden pitch count between polysilicon shapes of neighboring cells is reduced by 89%-100% in 130nm and 93%-100% in 90nm Edge placement error (EPE) count is also reduced by 80%-98% in 130nm and 83%-100% in 90nm AFCorr facilitates additional SRAF insertion by up to 74% for 130nm and 79% for 90nm In addition, AFCorr provides substantial improvement in CD control with negligible timing, area, or CPU overhead The advantages of AFCorr are expected to increase in future technology nodes

130 citations

Journal Article•DOI•
Level-specific lithography optimization for 1-Gb DRAM

[...]

Alfred K. K. Wong1, Richard A. Ferguson1, Scott M. Mansfield1, Antoinette F. Molless1, Donald J. Samuels1, R. Schuster, Alvin G. Thomas1 •
IBM1
01 Feb 2000-IEEE Transactions on Semiconductor Manufacturing
TL;DR: In this paper, a general level-specific optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175-and 150-nm ground rules, which is based on process latitude quantification using the total window metric, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics.
Abstract: A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

130 citations

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Frequently Asked Questions (12)
Q1. What are the contributions mentioned in the paper "Modeling opc complexity for design for manufacturability" ?

In this paper, the authors proposed a method for minimizing mask cost by relaxing OPC tolerances on standard cells, subject to meeting timing constraints. 

MCC for isolated context can be performed by running OPC followed by fracturing on individual standard cells for different IT, OT, SSIDE and FRAG. 

RET such as assist feature insertion and OPC are mandatory post tapeout steps to ensure printability of features in sub-90nm technology nodes. 

The authors then perform linear regression to fit the fracture count of standard cells as a function of layout parameters for each tolerance combination. 

Based on the fracture count data and layout parameter values for 15 cells, the authors perform regression studies to construct FC model using SPLUS7 software. 

FC model constructed for library MCC using a limited set of library cells for a given tolerance combination can predict the FC trend of up to 75% of cells in the library within 5% error. 

Doubling of layout data volume every technology node combined with aggressive RET is driving mask set cost to prohibitive levels. 

RET engineers can extend the presented models by adding other OPC parameters and use it for tuning OPC recipes and optical model parameters. 

59921W, (2005) · 0277-786X/05/$15 · doi: 10.1117/12.633416Proc. of SPIE Vol. 5992 59921W-1Characterization of mask cost and timing impact of different OPC tolerances is the basic step for a complete design-aware OPC flow. 

In the second approach, tolerance optimization is performed by choosing OPC tolerance combination specific to the standard cell or wire pattern by analyzing its impact on mask cost and design performance simultaneously. 

Even though the predicted FC differs from the actual FC, the trend in FC is useful for performing tolerance optimization, since the designer needs to be aware of the change in FC rather than the absolute value. 

In addition to the parametersProc. of SPIE Vol. 5992 59921W-2described above, fracture count also depends on OPC corrections performed at line-ends and corners.