Proceedings ArticleDOI
Enhanced simulation infrastructure for DFT ATPG simulations
Gautham Chandrashekar,R Dhanabal +1 more
- pp 1-4
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TLDR
This work aims to reduce the time required for regress pattern simulations by improving the simulation infrastructure and could observe reduction in the simulation time by 18–20 percentages in VCS tool.Abstract:
In the high demand of electronics such as mobile, tablets there is increase in the demand for high speed, good battery life and high storage. As it is common notion that power and speed always form inverse relation thus compromising on one factor is acceptable to customers. But area that is storage is a demanding factor and in order to achieve such high storage, Technology is shrinking down drastically (currently at 7nm) and expected to go even lower. With this shrinking of technology the need for detecting manufacturing defects becomes important and thus DFT architecture and regress pattern simulations become necessary factor. Our objective here is to reduce the time required for regress pattern simulations by improving the simulation infrastructure. Our results could observe reduction in the simulation time by 18–20 percentages in VCS tool.read more
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An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
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A method of fault analysis for test generation and fault diagnosis
H. Cox,Janusz Rajski +1 more
TL;DR: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits using a 16-valued logic system, GEMINI, and an extended fault model which includes stuck-at, stuck-open, and delay faults is used.
Journal ArticleDOI
Fault equivalence identification in combinational circuits using implication and evaluation techniques
TL;DR: Efficient techniques for identifying functionally equivalent faults in combinational circuits based on implication of faulty values, and evaluation of faulty functions in cones of dominator gates of fault pairs are presented.
Proceedings ArticleDOI
Comparison of optimized multi-stage clock gating with structural gating approach
Xin Man,Shinji Kimura +1 more
TL;DR: This paper enhances the optimization method including multi-stage clock gating and compares with structural gating approach and has obtained power reduction by 14.1% on average compared with single-stage structural method and by 10.8% compared with multi- stage structuralgating approach.
Proceedings ArticleDOI
Clock gating -A power optimization technique for smart card
TL;DR: The principle of the clock gating technology which is used to optimize power consumption of the smart card in RTL level is described and it turns out that the total power consumption has been reduced by 40% using the proposed method.