Patent
Evaluation method of fine pattern feature, its equipment, and method of semiconductor device fabrication
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TLDR
In this paper, the equipment acquires data of edge roughness over a sufficiently long area, integrates a components corresponding to a spatial frequency region being set on a power spectrum by the operator, and displays them on a length measuring SEM.Abstract:
Equipment extracts components of spatial frequency that need to be evaluated in manufacturing a device or in analyzing a material or process out of edge roughness on fine line patterns and displays them as indexes. The equipment acquires data of edge roughness over a sufficiently long area, integrates a components corresponding to a spatial frequency region being set on a power spectrum by the operator, and displays them on a length measuring SEM. Alternatively, the equipment divides the edge roughness data of the sufficiently long area, computes long-period roughness and short-period roughness that correspond to an arbitrary inspection area by performing statistical processing and fitting based on theoretical calculation, and displays them on the length measuring SEM.read more
Citations
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References
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Journal ArticleDOI
An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
TL;DR: In this article, an analytical model to represent line edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices is presented.
Proceedings ArticleDOI
Modeling line edge roughness effects in sub 100 nanometer gate length devices
TL;DR: In this article, a fast method to estimate the effects of line edge roughness is proposed, based upon the use of multiple 2D device "slices" sandwiched together to form a MOS transistor of a given width.
Proceedings ArticleDOI
Line edge roughness: characterization, modeling and impact on device behavior
J.A. Croon,G. Storms,S. Winkelmeier,Ivan Pollentier,M. Ercken,Stefaan Decoutere,Willy Sansen,Herman Maes +7 more
TL;DR: In this article, the impact of line edge roughness on MOSFET parameter fluctuations has been investigated and it has been shown that LER has no impact on 80 nm gate length transistors.
Study of Gate Line Edge Roughness Effects in 50 nm Bulk MOSFET Devices
TL;DR: In this paper, gate line edge roughness (LER) and its effect on electrical characteristics of 50nm bulk MOSFETs were studied using simulation, and the underlying mechanism of three significant LER effects on the electrical performance of advanced 50 nm gate length bulk devices.
Proceedings ArticleDOI
A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applications
K.K. Young,S.Y. Wu,C.C. Wu,C.H. Wang,C.T. Lin,J.Y. Cheng,M. Chiang,S.H. Chen,T.C. Lo,Y.S. Chen,J.H. Chen,L.J. Chen,S.Y. Hou,J.J. Law,T.E. Chang,C.S. Hou,J. Shih,S.M. Jeng,H.C. Hsieh,Y. Ku,T. Yen,Hun-Jan Tao,L.C. Chao,S. Shue,S.M. Jang,T.C. Ong,C.H. Yu,Mong-Song Liang,Carlos H. Diaz,J.Y.-C. Sun +29 more
TL;DR: In this article, a leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described, and a suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros.