Proceedings ArticleDOI
Experimental and theoretical study of layered tunnel barriers for nonvolatile memories
J. Buckley,B. De Salvo,G. Molas,Marc Gely,Simon Deleonibus +4 more
- pp 509-512
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TLDR
In this paper, the authors present an original study of the programming and retention characteristics of triple-layer SiO/sub 2/high-k/SiO/Sub 2/ tunnel barriers with a 5nm EOT.Abstract:
Engineering of the tunnel barrier of nonvolatile memories (NVM) is addressed in this paper. This work reports in its first part experimental results that show the improved field sensitivity of the gate current of MOS devices with SiO/sub 2//HfO/sub 2/ gate stacks compared to SiO/sub 2/ of identical electrical thickness (EOT). This improvement is justified by tunneling current simulations. The physical principle that is involved is applicable to symmetrical triple-layer tunnel barriers consisting of SiO/sub 2//HfO/sub 2//SiO/sub 2/ which could equally favor writing and erasing of NVM devices. The second part of this paper presents an original study of the programming and retention characteristics of triple-layer SiO/sub 2//high-k/SiO/sub 2/ tunnel barriers with a 5nm EOT. Our calculations allow to clearly view the influence of the high-k parameters on programming and data retention. According to our results, good characteristics are obtained for dielectrics with a 1.5eV conduction band offset compared to Si and for /spl epsiv/ /sub high-k/ /spl radic/m/sub high-k/ >(4m/sub high-k/: relative electron mass /spl epsiv/ /sub high-k/: relative dielectric constant). These conditions are verified by the physical parameters of HfO/sub 2/.read more
Citations
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References
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Journal ArticleDOI
Layered tunnel barriers for nonvolatile memory devices
TL;DR: Fowler-Nordheim tunneling of electrons through "crested" energy barriers (with the height peak in the middle) is much more sensitive to applied voltage than that through barriers of uniform height Calculations for trilayer barriers, with layer parameters typical for wideband gap semiconductors, have shown that by merely doubling the voltage, the tunnel current may be changed by more than 16 orders of magnitude as discussed by the authors.
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Band offsets of high dielectric constant gate oxides on silicon
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Journal ArticleDOI
Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices
B. De Salvo,Gerard Ghibaudo,G. Pananakakis,Pascal Masson,Thierry Baron,N. Buffet,A. Fernandes,B. Guillaumot +7 more
TL;DR: In this article, a thorough experimental and theoretical investigation of memory-cell structures employing discrete-trap type storage nodes, using either natural nitride traps or semiconductor nano-crystals, is presented.
Journal ArticleDOI
Stacked high-ε gate dielectric for gigascale integration of metal–oxide–semiconductor technologies
P. K. Roy,I. C. Kizilyalli +1 more
TL;DR: In this paper, the authors proposed a thermally grown SiO2(15 A) and Ta2O5(30 A) dielectric with improvements in leakage, tunneling, charge trapping behavior, and interface substructure.
Proceedings ArticleDOI
Multilayer tunneling barriers for nonvolatile memory applications
TL;DR: In this article, a tunnel barrier consisting of two materials with different dielectric constant is demonstrated to show that improved programming and/or erasing performance is obtained compared to conventional oxide layers.