# Exploiting Posit Arithmetic for Deep Neural Networks in Autonomous Driving Applications

TL;DR: It is argued that a new representation for floating point numbers called Posit is particularly advantageous, allowing for a better trade-off between computation accuracy and implementation complexity.

Abstract: This paper discusses the introduction of an integrated Posit Processing Unit (PPU) as an alternative to Floating-point Processing Unit (FPU) for Deep Neural Networks (DNNs) in automotive applications. Autonomous Driving tasks are increasingly depending on DNNs. For example, the detection of obstacles by means of object classification needs to be performed in real-time without involving remote computing. To speed up the inference phase of DNNs the CPUs on-board the vehicle should be equipped with co-processors, such as GPUs, which embed specific optimization for DNN tasks. In this work, we review an alternative arithmetic that could be used within the co-processor. We argue that a new representation for floating point numbers called Posit is particularly advantageous, allowing for a better trade-off between computation accuracy and implementation complexity. We conclude that implementing a PPU within the co-processor is a promising way to speed up the DNN inference phase.

## Summary (3 min read)

### Introduction

- For datafusion a grid-based approach may be used to determine the occupancy probability (Bayesian approach) of a cell, or the belief function (Dempster-Shafer approach), by evaluating the current sensor reading and the history from past cycle [11].
- To accelerate DNN computing in automotive applications, this paper discusses the introduction of the Posit Processing Unit (PPU) as alternative to the Floating-point Processing Unit (FPU).
- In Sections IV the authors argue that 16- bit Posits can replace conventional FPUs, since they are more accurate if the same number of bits is used.

### II. ALTERNATIVE REAL NUMBER REPRESENTATIONS

- Representing real numbers in electronic computers requires the selection of a method to map real numbers into a sequence of bits.
- Hardware realization of specific elementary functions are also desired.

### A. Type-I Unums

- Type-I uniform numbers have been introduced in Gustafson’s book [20].
- While the sign, exponent, and fraction bit fields take their definition from IEEE 754, the exponent and fraction field lengths vary automatically, from a single bit up to some user specified maximum .
- Type-I Unums have been recently implemented in hardware, on FPGA [16, 22], also known as Hardware implementations.
- This is due to both the variable length operands and the interval arithmetic, which is more complex than arithmetic between floats.
- The authors believe that Type-I Unums are not particularly appealing for DNN in autonomous driving applications, due to the disadvantages mentioned above.

### B. Type-II Unums

- Type-II Unums have been introduced again by Prof. Gustafson in [23].
- Here the key idea was to represent both exact real numbers and the open interval between two consecutive exact real numbers represented.
- In addition, computing the opposite and the reciprocal takes the same time Disadvantages:.
- The SORN approach needs look-up tables requiring large amounts of ROM/RAM.
- Unums have not been implemented in hardware yet.

### C. Other formats

- Jorgensen has recently patented a format which retains the correct bounds after each computation and the corresponding hardware [24].
- This proposal is another evidence of the need of novel formats for real numbers and novel hardware implementations, and, although interesting, is too similar to Type-I Unums.
- On the other hand Type-I Unums are free from patents rights.
- In conclusion of this section, none of these newly proposed floating point representations are satisfactory for DNNs.
- On the contrary, the Posit data format, explained in the next section has promising properties.

### III. THE POSIT REPRESENTATION

- Posits are a by-product of the Type-II Unums numbers described in previous section and they have been introduced very recently in [25], again by Gustafson.
- Please observe how the two Posits representations shown in the figure have a different number of bits reserved for the fraction field (8 and 9, respectively), having different lengths for the regime fields (4 vs 3).
- Please notice that the floating-point standard wastes a lot of representations for NaNs, which also make the hardware for comparing floats very complex.
- Thus comparing two Posits can be done in ALU (by type re-casting to signed integers): negative Posits are expressed using complement two as integers, and the other three fields allow direct ordering.

### A. Dimensioning Posits

- As mentioned the Posit representation is parametrized over the total number of bits to use and the number of them to reserve to the exponent.
- Depending on the task at hand, these two numbers can chosen accordingly.
- Thus the authors know that 16-bit Posits are sufficient too.
- In addition the authors observe that the Posit representation is compatible with the flexpoint idea introduced in [15].
- Indeed, it is possible to create Posits tensors that share an extra exponent field.

### IV. HARDWARE IMPLEMENTATION ISSUES

- The implementation of a PPU will take advantage of the operations over Posits that can be traced back to three main levels of Posit representation: i) binary form, ii) decoded form, and iii) expanded form.
- The first one is the binary representation of Posits discussed so far that can be used for some operations, with the effect of fastest speed and minimal complexity.
- The second form decodes the Posit in the three components of regime, exponent and fraction by parsing the variable length encoding of the regime field.
- Inversion, doubling and halving can be efficiently computed by working on this intermediate representation, in addition to the fundamental arithmetic operations when fraction is zero.
- The third level requires a more sophisticated logic that, anyway, in comparison to IEEE floating points, can take advantage of the separation between regime and exponent parts.

### B. Specific DNN functions to implement in hardware

- In existing custom hardware for Tensor operations (e.g. Nvidia Tensor units and Google TPU) there are specific operations that are structured in hardware due to their repetitive nature.
- In the following the authors are considering some fundamental DNN operations that can take advantage of Posit representation and that can be directly executed.
- DNN functions that are interesting to implement in hardware are the following:.

### C. PPU emulation library

- Posits library has been implemented using a C++ template library parametrized over Posit length and exponent length.
- The implementation takes advantage of the representation levels discussed in Section IV.
- Moreover level 3 operations of small Posits (e.g. less than 14 bits) can be implemented in the library using lookup tables.
- The use of a look-up table is interesting for those applications requiring a low precision and for those computers having sufficient cache memory, like current desktop PCs.
- In particular the library can be used for working with the C++ Eigen template matrices library [29].

### D. Summary: the advantages of Posits over Floats

- More in general, the authors confirm that Posits are an interesting data format for low-precision arithmetic.
- In particular, using Posit16 the authors are widening the range of applications for which 16 bits are enough, thus saving bandwidth, storage and energy consumption in comparison to Float32.

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##### Frequently Asked Questions (2)

###### Q2. What are the future works mentioned in the paper "Exploiting posit arithmetic for deep neural networks in autonomous driving applications" ?

As further evolution of the work the authors are analyzing whether the use of Posits can be helpful even during the training phase of DNNs. Such servers can be equipped with co-processors as well.