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Proceedings ArticleDOI

Exploiting shared scratch pad memory space in embedded multiprocessor systems

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TLDR
An optimization algorithm is proposed that targets the reduction of extra off-chip memory accesses caused by inter-processor communication by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors.
Abstract
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors. Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and 24.3% on average) on a four-processor embedded system. The results also show that the proposed strategy is robust in the sense that it gives consistently good results over a wide range of several architectural parameters.

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Citations
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Journal ArticleDOI

Power reduction techniques for microprocessor systems

TL;DR: It is concluded that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level and it remains too early to tell which techniques will ultimately solve the power problem.
Proceedings ArticleDOI

Integrated scratchpad memory optimization and task scheduling for MPSoC architectures

TL;DR: This work designs an integrated task mapping, scheduling, SPM partitioning, and data allocation technique based on Integer Linear Programming (ILP), and shows that integrated task schedul-ing and SPM optimization improves performance by up to 80% for embedded applications.
Proceedings ArticleDOI

A post-compiler approach to scratchpad mapping of code

TL;DR: This paper proposes an optimal scratchpad mapping approach for code segments, which has the distinctive characteristic of working directly on application binaries, thus requiring no access to either the compiler or the application source code - a clear advantage for legacy or proprietary, IP-protected applications.
Proceedings ArticleDOI

Polynomial-time algorithm for on-chip scratchpad memory partitioning

TL;DR: An algorithm to optimally solve such a mapping problem by means of Dynamic Programming applied to a synthesizable hardware architecture by mapping segments of external memory to physically partitioned banks of an on-chip SPM; this architecture provides significant energy savings.
Journal ArticleDOI

Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad Memory

TL;DR: A loop pipeline scheduling algorithm known as Rotation Scheduling with Variable Partitioning (RSVP) is presented to improve overall throughput and propose two variable partitioning heuristics based on an initial schedule: High Access Frequency First (HAFF)Variable partitioning and Global View Prediction (GVP) variable partitioned.
References
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Book

Compilers: Principles, Techniques, and Tools

TL;DR: This book discusses the design of a Code Generator, the role of the Lexical Analyzer, and other topics related to code generation and optimization.
Book

High-Performance Compilers for Parallel Computing

TL;DR: This book discusses Programming Language Features, Data Dependence, Dependence System Solvers, and Run-time Dependence Testing for High Performance Systems.
Book

Design of High-Performance Microprocessor Circuits

TL;DR: The design of next generation microprocessors in deep submicron CMOS technologies is covered, and a broad range of circuit styles and VLSI design techniques are covered, an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers.
Journal ArticleDOI

Energy dissipation in general purpose microprocessors

TL;DR: It is found that careful design reduced the energy dissipation by almost 25% and methods of reducing energy consumption that do not lead to performance loss, and methods to reduce delay by exploiting instruction level parallelism are explored.
Book

Dependence analysis for supercomputing

TL;DR: This chapter discusses one-Dimensional Arrays, Single Loops, and Dependence Tests, which are tests of the theory of Dependence on Vectors and its application to Systems of Equations.
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