Exploration of Multi-thread Processing on XILKERNEL for FPGA Based Embedded Systems
29 May 2013-pp 58-65
TL;DR: This work on resource estimation for the various task scheduling policies using XILKERNEL is first of its kind on resource utilization for a given embedded RTOS environment.
Abstract: The present day FPGA (Field Programmable Gate Array) technology is capable to design high performance embedded systems based on its soft core (MicroBlaze) and hard core (PowerPC) processors, embedded memories and other IP cores. Embedded system design demands use of limited hardware resources with as minimum power as possible while providing higher throughput. One way to decrease the complexity of application is to use a thread-oriented design where a process is divided into a number of manageable pieces known as threads. Each thread is responsible for some part of the application, thus providing multitasking. Further, for real-time task execution we need to have an efficient RTOS (Real Time Operating System) infrastructure on FPGA. Deciding a particular scheduling algorithm for thread execution requires the knowledge of resource utilization for the specific scheduling policy. Hence, a proper exploration of the various thread scheduling algorithms in terms of resource utilization, for a given embedded platform is of much importance. The incorporation of XILKERNEL RTOS in FPGA is a latest facility. Though there exists a few research work on analyzing the resource requirement in multitasking scenario for a given embedded RTOS environment, our work on resource estimation for the various task scheduling policies using XILKERNEL is first of its kind. Implementation of real-time scheduling algorithm like RMS on XILKERNEL has also been endeavored, using OS virtualization, since it is not directly supported by the kernel of XILKERNEL.
Citations
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TL;DR: A system-level observation framework that provides minimally intrusive methods for dynamically monitoring and analyzing deeply integrated hardware and software components within embedded systems.
Abstract: As the complexity of embedded systems rapidly increases, the use of traditional analysis and debug methods encounters significant challenges in monitoring, analyzing, and debugging the complex interactions of various software and hardware components. This situation is further exacerbated for in-situ debugging and verification in which traditional debug and trace interfaces that require physical access are unavailable, infeasible, or cost prohibitive. In this article, we present a system-level observation framework that provides minimally intrusive methods for dynamically monitoring and analyzing deeply integrated hardware and software components within embedded systems. The system-level observation framework monitors hardware and software events by inserting additional logic for detecting designer-specified events within hardware cores to observe complex interaction across hardware and software boundaries at runtime, and provides visibility for monitoring complex execution behavior of software applications without affecting the system execution.
9 citations
Cites methods from "Exploration of Multi-thread Process..."
...When utilizing Xilinx’s xilkernel [69][83], the current PID is provided by the trace interface signal trace_pid_reg....
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03 Jul 2014
TL;DR: An effort is made to carry out performance comparisons of two real-time operating systems, based on their scheduling latencies, and FreeRTOS and ChibiOS/RT deployed onto CORTEX-M3 processors are chosen for this purpose.
Abstract: In hard real time systems, determinism and predictability of time are important aspects that need to be considered in the execution of a given task. It is a well-known fact that the task execution time depends on scheduling latency which in turn depends on the capability of Real Time Operating Systems (RTOS) scheduler. Hence it is clear that scheduling latency is an important parameter of RTOS that specifies its performance. Thus keeping an eye on recently available Real Time Operating Systems, an effort is made in this work to carry out performance comparisons of two real-time operating systems, based on their scheduling latencies. FreeRTOS and ChibiOS/RT deployed onto CORTEX-M3 processors are chosen for this purpose.
5 citations
Cites background from "Exploration of Multi-thread Process..."
...In scheduling mechanism, scheduling latency is the time gap between the execution of last instruction of interrupt service routine and the execution of first instruction of respective task[3]....
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03 Jun 2022
TL;DR: The obtained results show that the proposed 4-core FPGA architecture stands well both in terms of timing and efficiency metrics, and could benefit the design and development of real-time systems utilizing operating systems withreal-time support, in emerging areas such as embedded devices in real- time control.
Abstract:
The challenges in real-time multithreading, particularly in the efficiency of multithreaded applications running concurrently on multiple cores, have evolved significantly due to the increase of IoT, cloud and edge computing applications. The continuous increase on cores depth adds further research issues about the efficiency of such multicore systems and their applications. Therefore, further research is still required.
Multicore systems can achieve higher performance running in parallel multiple multithreaded applications. However, efficient parallelisation of multiple threads among many cores is not an easy task. Field Programmable Gate Arrays (FPGAs) is a preferred technology for the rapid design and experimentation with such architectures, based primarily on softcore processors.
The purpose of this research is to investigate the efficiency of running in parallel and concurrently multithreaded applications on a 4-core FPGA multicore architecture.
The design of a 4-core FPGA architecture is implemented with Nios II/f soft processors on a Cyclone IV series chip, having real-time Linux operating system (OS) support. A multithreaded application with specific compute-intensive tasks is developed in C, and is used to obtain measurements in specific efficiency metrics under different core configurations.
The reliability of the proposed 4-core FPGA architecture is validated against 4-core and 2-core development platforms, respectively on a Raspberry Pi4 and BeagleBone AI single board computers. The results have been analysed and evaluated upon performance metrics, including execution time, response time, speedup, and cores usage. The experimental tests demonstrate the validity and efficiency of the approach on using an FPGA for experimentations with multithreaded applications.
The obtained results show that the proposed FPGA architecture stands well both in terms of timing and efficiency metrics. Execution times are about 50% lower and the average speedup at 21% is fairly close to that of 33% for the Raspberry Pi4, and higher than BeagleBone AI (10%). The proposed measurements approach and evaluation methodology could benefit the design and development of real-time systems utilizing operating systems with real-time support, in emerging areas such as embedded devices in real-time control.
References
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TL;DR: In this article, Abraham Silberschatz and Peter Galvin discuss key concepts that are applicable to a variety of operating systems and present a large number of examples taken from common operating systems, including WindowsNT and Solaris 2.
Abstract: From the Publisher:
This best-selling book, now in its fifth edition, provides a solid theoretical foundation for understanding operating systems. Authors Abraham Silberschatz and Peter Galvin discuss key concepts that are applicable to a variety of systems. They also present a large number of examples taken from common operating systems, including WindowsNT and Solaris 2. This book teaches general principles in operating systems while giving the teacher and students the flexibility to choose the implementation system.
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TL;DR: An investigation is conducted of two protocols belonging to the priority inheritance protocols class; the two are called the basic priority inheritance protocol and the priority ceiling protocol, both of which solve the uncontrolled priority inversion problem.
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12 Nov 2007
TL;DR: The incurred time and area overheads are investigated, especially for inter-thread communication across the hardware/-software boundary, and a case study demonstrating the feasibility of the RTOS-centric design approach is presented.
Abstract: Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodologies have not kept up with the rise in complexity of the target hardware. In particular, there is little overlap between the programming model for embedded software running on a real-time operating system and the programming model for digital logic. In this paper, we present the operating system ReconOS which supports both software and hardware threads with a single unified programming model. ReconOS is based on eCos, a widely-used real-time operating system (RTOS). We investigate the incurred time and area overheads, especially for inter-thread communication across the hardware/-software boundary, and present a case study demonstrating the feasibility of the RTOS-centric design approach.
88 citations
"Exploration of Multi-thread Process..." refers background in this paper
...Index Terms—FPGA;MicroBlaze;RTOS;XILKERNEL;Thread I. INTRODUCTION As the complexity of embedded system grows, there is a strong need of high performance computing infrastructure....
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...Thread A is attached to a named shared memory segment and writes data to it....
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...In FPGA based embedded system there are many third party RTOSes such as Vxworks, Nucleus, eCOS, Threadx....
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...There are many RTOS environments e.g. Vxworks, Reconos, ecos, ThraedX, Xilkernel etc. − all support multi-thread processing Recent R&D initiatives have focused on suitable multithreaded implementation on FPGA based embedded systems, keeping track of the need of modern applications....
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...A thread is like a function that has its own stack, and a Thread Control Block (TCB) [8]....
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04 Apr 2005
TL;DR: The design and implementation of a software reconfigurable multiprocessor system, based on Xilinx MicroBlaze softcore processors, and a real application in the automotive domain implemented on a XILinx Virtex-II 3000 FPGA is used to present results.
Abstract: Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. When designing a system that includes this feature it has to be made sure, that no signal lines cross the border to other reconfigurable regions. The complex modular design flow to generate partial bitstreams and the need of macros for physical interconnection of IP-Cores causes the necessity to investigate in alternatives. This paper describes the design and implementation of a software reconfigurable multiprocessor system, based on Xilinx MicroBlaze softcore processors. A real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA is used to present results.
45 citations
"Exploration of Multi-thread Process..." refers background in this paper
...There are many RTOS environments e.g. Vxworks, Reconos, ecos, ThraedX, Xilkernel etc. − all support multi-thread processing Recent R&D initiatives have focused on suitable multithreaded implementation on FPGA based embedded systems, keeping track of the need of modern applications....
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19 Apr 2010
TL;DR: A special purpose operating system, called CAPOS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the service of priority-based access scheduling, hardware task mapping and resource management.
Abstract: Operating systems traditionally handle the task scheduling of one or more application instances on a processor like hardware architecture. Novel runtime adaptive hardware exploits the dynamic reconfiguration on FPGAs, where hardware blocks are generated, started and terminated. This is similar to software tasks in well established operating system approaches. The hardware counterparts to the software tasks have to be transferred to the reconfigurable hardware via a configuration access port. This port enables the allocation of hardware blocks on the FPGA. Current reconfigurable hardware, like e.g. Xilinx Virtex 5 provide two internal configuration access ports (ICAPs), where only one of these ports can be accessed at one point of time. In e.g. a multiprocessor system on an FPGA, it can happen that multiple instances try to access these ports simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled by a special purpose operating system running on an embedded processor. This special purpose operating system, called CAPOS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the service of priority-based access scheduling, hardware task mapping and resource management.
30 citations
"Exploration of Multi-thread Process..." refers background in this paper
...There are many RTOS environments e.g. Vxworks, Reconos, ecos, ThraedX, Xilkernel etc. − all support multi-thread processing Recent R&D initiatives have focused on suitable multithreaded implementation on FPGA based embedded systems, keeping track of the need of modern applications....
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