Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs
01 Aug 2012-IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers Inc.)-Vol. 33, Iss: 9, pp 1306-1308
TL;DR: In this article, a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements is presented, and the technique of determining isothermal condition using only the selfheating (thermal) dominated range of the spectrum.
Abstract: In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.
Citations
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TL;DR: This letter investigates the RF performance of a negative capacitance FinFET using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices, and finds that NC-FinFET’s cut-off frequency is a function of LaTeX, and observes that the self-heating effect in NC-finFET increases with increase ininline-formula.
Abstract: In this letter, we have investigated the RF performance of a negative capacitance FinFET (NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices. This physics-based RF model is then coupled self-consistently with the Landau-Khalatnikov equation to obtain the RF NC-FinFET model. For the first time, we report, here, the impact of ferroelectric thickness ( ${t}_{\textit {fe}}$ ) scaling on RF performance of NC-FinFET and find that NC-FinFET’s cut-off frequency ( ${f}_{\text {T}}$ ) is a function of ${t}_{\textit {fe}}$ . We also observe that the self-heating effect in NC-FinFET increases with increase in ${t}_{\textit {fe}}$ , mainly due to increase in DC current, which can be easily compensated by decreasing supply voltage. Finally, we show that NC-FinFET can achieve similar analog/RF performance as the base FinFET, even at a reduced ${V}_{\mathrm{ DD}}$ .
45 citations
Cites methods from "Extraction of Isothermal Condition ..."
...Therefore, to extract thermal parameters Rth and Cth , we have fitted nth-order thermal network (N/W) model to gds( f ) and Cdd( f ) measurement plots till fiso (∼110MHz) [27]....
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02 Apr 2017
TL;DR: An overview of the research on self-heating in transistors is presented and modulators, measurement schemes, spatio-temporal sensitivities, and impacts on performance and reliability are discussed.
Abstract: On advanced technology nodes, increases in power density, non-planar architectures and different material systems can exacerbate local self-heating due to active power dissipation, which can affect device performance and reliability in various ways This paper presents an overview of the research on self-heating in transistors and discusses modulators, measurement schemes, spatio-temporal sensitivities, and impacts on performance and reliability As the industry continues to scale dimensions and power densities, the significance of self-heating effects will continue to grow, and a robust frame-work to fully assess it, and deal with its impacts to circuits and IP blocks are essential
39 citations
TL;DR: In this article, the performance of the BSIM-IMG model for fully depleted silicon-on-insulator (FDSOI) transistors is discussed with experimental data.
Abstract: In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.
34 citations
Cites background or methods from "Extraction of Isothermal Condition ..."
...The model shows good agreement with experimental data in all regions of operation, which implies accurate modeling of sub-modules like mobility and current saturation....
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...In this section, we have discussed the variation of Real Y22, CGG , and Rg in a wide frequency range and their impact on the analog/RF FoM....
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...As the frequency of the applied small signal increases, the device temperature gradually stops following the applied signal and remains effectively constant for frequency, fiso > 1/Rth ∗ Cth [25]....
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TL;DR: In this paper, the authors present an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications, mainly focusing on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies fT and fmax.
Abstract: This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies fT and fmax. Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, gm–Av analogue metric is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that fT of 280 GHz and fmax of 250 GHz are reachable in the shortest devices. These values are compared to those of the first generation of UTBB devices through the effect of parasitic elements.
33 citations
Cites methods or result from "Extraction of Isothermal Condition ..."
...Extracted thermal resistance was compared with the thermal resistance reported in UTB and UTBB devices [3], [13], [16], [17] and presented in Figure 7....
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...Results from [13], [16], [17] were obtained experimentally while [3] is based on numerical simulations....
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TL;DR: A review of the history and trends of local self-heating effects, the characterization techniques thereof, and the manifestations, sensitivities, and impacts of this heating on reliability mechanisms is presented in this article.
Abstract: The march toward dimensional scaling and higher performance has led the semiconductor industry to consider nonplanar topologies and different material systems. These choices have led to an increase in the local power dissipation and, correspondingly, a rise in the local self-heating (SH). This article is a review of the history and trends of SH effects, the characterization techniques thereof, and the manifestations, sensitivities, and impacts of this heating on reliability mechanisms. Future pathways are also highlighted to indicate the challenges that exist for CMOS technologies.
33 citations
References
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TL;DR: In this article, the authors measured and modeled self-heating in SOI nMOSFETs under static operating conditions and showed that the measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation.
Abstract: Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >
312 citations
TL;DR: In this paper, a 40nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide.
Abstract: A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.
202 citations
TL;DR: In this paper, the authors characterized the dynamic self-heating effect in n-channel SOI FinFETs, and the dependence of thermal resistance on finFET geometry is discussed.
Abstract: Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.
81 citations
"Extraction of Isothermal Condition ..." refers background or methods in this paper
...The ac output conductance technique is an excellent innovation [4], [5] and has been improved by extension to S-parameter-based two-port RF measurement [9]–[11]....
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...Reference [11] obtains the thermal time constant from an empirical choice of isothermal frequency....
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IBM1
TL;DR: In this paper, a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates is presented.
Abstract: We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field).
81 citations
"Extraction of Isothermal Condition ..." refers background in this paper
...Thin buried oxide (BOX) gives an extra flexibility in terms of improved short channel effects [2] and threshold voltage (Vth) adjustment [3] through controlled back gate bias....
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16 Sep 2003
TL;DR: In this article, a simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed, and it is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less than 2 /spl mu/s and duty factors lower than 1:100.
Abstract: This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.
80 citations
"Extraction of Isothermal Condition ..." refers methods in this paper
...The ac output conductance technique of self-heating measurement [4], [5] replaced pulsed measurement technique [6], [7] for its various shortcomings such as significant heating in the initial finite rise time of the pulse....
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