Journal ArticleDOI
Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements
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TLDR
In this paper, an extraction method to obtain the induced gate noise (i~/sub g/~/sup 2/~) channel noise and their cross correlation in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements.Abstract:
An extraction method to obtain the induced gate noise (i~/sub g/~/sup 2/~) channel noise (i~/sub d/~/sup 2/~), and their cross correlation (i~/sub g/~i~/sub d/~*~) in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements. In addition, the extracted induced gate noise, channel noise, and their correlation in MOSFETs fabricated in 0.18-/spl mu/m CMOS process versus frequencies, bias conditions, and channel lengths are presented and discussed.read more
Citations
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Journal ArticleDOI
A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers
TL;DR: A gain control mechanism is introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.
Journal ArticleDOI
Channel noise modeling of deep submicron MOSFETs
Chih-Hung Chen,M.J. Deen +1 more
TL;DR: In this article, a new channel noise model using the channel length modulation (CLM) effect was proposed to calculate the channel noise of deep submicron MOSFETs.
Journal ArticleDOI
MOSFET modeling for RF IC design
TL;DR: In this paper, a high-frequency (HF) modeling of MOSFETs for radiofrequency (RF) integrated circuit (IC) design is discussed by accounting for important physical effects at both dc and HF.
BookDOI
Device Modeling for Analog and RF CMOS Circuit Design: Ytterdal/Device
TL;DR: The BSIM4 MOSFET model as discussed by the authors has been used for accurate distortion analysis of passive devices in CMOS technologies, and the EKV model has also been used to model process variations and device mismatches.
Journal ArticleDOI
A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects
C. Kromer,G. Sialm,C. Berger,Thomas Morf,Martin L. Schmatz,Frank Ellinger,Daniel Erni,Gian-Luca Bona,Heinz Jäckel +8 more
TL;DR: This work presents the highest serial data rate for CMOS transceiver arrays and the lowest power consumption per data rate reported to date.
References
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Book
Noise in solid state devices and circuits
TL;DR: In this paper, the authors propose a method to generate 1/f noise noise in particular Amplifier Circuits Mixers by using thermal noise shot and flicker noise, respectively.
Journal ArticleDOI
MOS transistor modeling for RF IC design
Christian Enz,Yuhua Cheng +1 more
TL;DR: In this article, the authors present the basis of the modeling of the MOS transistor for circuit simulation at RF and present a physical equivalent circuit that can be easily implemented as a Spice subcircuit.
Journal ArticleDOI
A 5-GHz CMOS wireless LAN receiver front end
TL;DR: In this paper, a 12.4-mW front end for a 5GHz wireless LAN receiver fabricated in a 0.24/spl mu/m CMOS technology is presented, which consists of a low-noise amplifier, mixers, and an automatically tuned third-order filter controlled by a low power phase-locked loop.
Journal ArticleDOI
Gate noise in field effect transistors at moderately high frequencies
TL;DR: In this article, the gate noise of a field effect transistor increases with increasing frequency and is attributed to the thermal noise of the conducting channel and is caused by the capacitive coupling between the channel and the gate.
Journal ArticleDOI
Nyquist's and Thevenin's Theorems Generalized for Nonreciprocal Linear Networks
TL;DR: In this article, it was shown that an N−node non-reciprocal linear network, with a system of internal thermal noise generators at temperature T, is equivalent to the source-free network together with a set of correlated nodal current generators, with infinite internal impedance, such that 〈iris*〉Avdν=2kT(yrs+ysr*)dν where yrs is an element of the network admittance matrix and ir is the rth nodal noise current with frequency v.