Extremely high-density capacitors with ald high-k dielectric layers
01 Jan 2006-pp 17-28
TL;DR: In this paper, the authors describe the deposition of high-k dielectric layers, Al2O3, Ta2O5, HfO2, etc, in high aspect ratio pores aiming for a higher capacitance density at a given breakdown voltage.
Abstract: This paper describes the deposition of high-k dielectric layers, Al2O3, Ta2O5, HfO2, etc, in high aspect ratio pores aiming for a higher capacitance density at a given breakdown voltage. The most emerging technology to achieve this appears to be Atomic Layer Deposition, ALD. However, applying ALD to wafers with deep pores leads to additional challenges to be dealt with. Apart from e.g. roughness on the sidewalls of the pores, leading to undesired lower breakdown voltages, and native oxide layers, leading to undesired lower relative dielectric constants, carrying out ALD on wafers with a large topography needs careful consideration of the ALD process. An appropriate step coverage and proper microstructure (morphology and texture) are necessary to achieve good insulating layers, but are certainly not obvious! This paper addresses issues we ran into in our challenge to realize very high capacity densities (preferably > 200 nF/mm) with sufficient insulating quality.
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TL;DR: In this paper, an atomic-layer deposition (ALD) was used to achieve an ultra-high capacitance density of 440 at a breakdown voltage VDB > 6 V on a silicon substrate containing high-aspect-ratio macropore arrays.
Abstract: ldquoTrenchrdquo capacitors containing multiple metal-insulator-metal (MIM) layer stacks are realized by atomic-layer deposition (ALD), yielding an ultrahigh capacitance density of 440 at a breakdown voltage VDB > 6 V. This capacitance density on silicon is at least 10times higher than the values reported by other research groups. On a silicon substrate containing high-aspect-ratio macropore arrays, alternating MIM layer stacks comprising high-k Al2O3dielectrics and TiN electrodes are deposited using optimized ALD processing such that the conductivity of the TiN layers is not attacked. Ozone annealing subsequent to each Al2O3 deposition step yields significant improvement of the dielectric isolation and breakdown properties.
146 citations
Cites background or methods from "Extremely high-density capacitors w..."
...layer uniformity, pulse/purge ratios have been adapted [11], and precursor types, preferably without H2O, have been optimized....
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...adaptation of the ALD process is required [11]....
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Patent•
01 Nov 2007TL;DR: In this paper, a capacitor device having a first conductive element and a second conductive elements is described. The capacitor includes a porous membrane disposed between the first and second conductives, and a conductive material is disposed inside the pores and in contact with the first conductives.
Abstract: A capacitor device having a first conductive element and a second conductive element The capacitor includes a porous membrane disposed between the first and second conductive elements The capacitor has pores included in the porous membrane extending from the first conductive element to the second conductive element, and a conductive material is disposed inside the pores and in contact with the first conductive element
47 citations
TL;DR: In this article, a self-powered metal-oxide semiconductor field effect transistor (MOSFET) gate driver is proposed to allow flexible or even permanent ON state time duration operation.
Abstract: An original method to power supply gate drivers has been previously developed. This solution takes advantage of power switch commutations to recharge periodically a storage capacitor, and then to create the necessary floating power supply, useful for many power electronic converters. It is a low cost solution that can be integrated, but it presents some disadvantages: the storage capacitor must be adjusted with respect to the ON state time duration, and a permanent ON state operation is forbidden. Moreover, with the existing solution, a low frequency operation is problematic, because a large storage capacitor would be required. The proposed work presents here an improvement of the solution, in order to a allow flexible or even permanent ON state time duration operation of a self powered metal oxide semiconductor field effect transistor, using few additional elements. This solution exhibits unexpected and fairly good efficiency levels and presents a high ability for a simple implementation and monolithic integration. Added to these new features, smaller values for the storage capacitor can be used for this self powered driver power supply, allowing from very low up to high frequency operation and high duty cycle operation. This particular solution may simplify the integration of the storage capacitor, in the same substrate as the main switch and its self powering circuits.
17 citations
Cites background from "Extremely high-density capacitors w..."
...Last efforts have to be done on capacitor integration: large values of capacitors can’t be integrated today (best results are in the range of a few tens nanofarad under 15 V from the literature and they require either a large surface or a deep trench shape [20], [21]), but there are two solutions: the capacitor can be integrated with an hybrid method and be mounted on main self powered switch, or integrated in main silicon substrate....
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TL;DR: In this article, the authors considered the need for high-capacity capacitors of micron size to meet the challenge of deep-subvoltage nanoelectronics and related technologies, and the necessity of developing all-solid-state impulse micron-sized supercapacitors on the basis of advanced superionic conductors.
Abstract: The decrease of energy consumption per 1 bit processing (e) and power supply voltage (Vdd) of integrated circuits (ICs) are long-term tendencies in micro- and nanoelectronics. In this framework, deep-sub-voltage nanoelectronics (DSVN), i.e., ICs of ~1011–1012 cm-2 component densities operating near the theoretical limit of e, is sure to find application in the next 10 years. In nanoelectronics, the demand on high-capacity capacitors of micron sizes sharply increases with a decrease of technological norms, e and Vdd. Creation of high-capacity capacitors of micron size to meet the challenge of DSVN and related technologies is considered. The necessity of developing all-solid-state impulse micron-sized supercapacitors on the basis of advanced superionic conductors (nanoionic supercapacitors) is discussed. Theoretical estimates and experimental data on prototype nanoionic supercapacitors with capacity density δC ≈ 100 μF/cm2 are presented. Future perspectives of nanoionic devices are briefly discussed.
13 citations
20 Jun 2011
TL;DR: In this paper, a technique to conformally coat solution-derived electrodes and dielectric films over through-silicon-Via (TSV) or through-Silicon Trench (TST) structures is presented.
Abstract: This paper explores and demonstrates a novel technique to conformally coat solution-derived electrodes and dielectric films over Through-Silicon-Via (TSV) or Through-Silicon Trench (TST) structures. In this technique, precursor solution for electrode or dielectric coatings is dispensed on the top of a TSV wafer and infiltrated through the via by creating a pressure gradient. Two material systems used in capacitors, Lanthanum Nickel Oxide (LNO) as electrode and Lead Zirconate Titanate (PZT) as dielectric, were deposited on the TSV surfaces using this technique. SEM cross-section analysis showed that the vacuum-infiltration can be extended to conformally coat on trenches with aspect ratios of greater than 5. A planar capacitor with density of 3 μF/cm2 and low leakage was fabricated to demonstrate the material compatibility. Using this technique, a trench capacitor device can be fabricated with an all-solution coating process, without involving any expensive deposition tools. This can thus eliminate costly platinum electrodes that are frequently required to yield high permittivity PZT films. This technique can also address the through-put limitations of today's conformal deposition technologies such as sputtering, Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD). The tool and process can also be applied to other 3D silicon structures where conformal ceramic coatings are needed.
10 citations
References
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Patent•
27 Nov 1993TL;DR: In this paper, anisotropic plasma etching of silicon is used to provide laterally defined recess structures therein through an etching mask employing a plasma, the method including anisotropically-plasmine etching, polymerizing in a polymerizing step at least one polymer former contained in the plasma onto the surface of the silicon during which the surfaces that were exposed in a preceding etching step are covered by a polymer layer thereby forming a temporary etching stop.
Abstract: A method of anisotropic plasma etching of silicon to provide laterally defined recess structures therein through an etching mask employing a plasma, the method including anisotropic plasma etching in an etching step a surface of the silicon by contact with a reactive etching gas to removed material from the surface of the silicon and provide exposed surfaces; polymerizing in a polymerizing step at least one polymer former contained in the plasma onto the surface of the silicon during which the surfaces that were exposed in a preceding etching step are covered by a polymer layer thereby forming a temporary etching stop; and alternatingly repeating the etching step and the polymerizing step. The method provides a high mask selectivity simultaneous with a very high anisotropy of the etched structures.
934 citations
TL;DR: In this paper, the effect of pore surface roughness on Knudsen diffusion in nanoporous media is investigated by dynamic Monte Carlo simulations and analytical calculations, where a conceptual difference is found between the roughness dependence of the macroscopic, transport diffusivity and the microscopic, self-diffusivity, which is reminiscent of diffusion in zeolites.
Abstract: The effect of pore surface roughness on Knudsen diffusion in nanoporous media is investigated by dynamic Monte Carlo simulations and analytical calculations. A conceptual difference is found between the roughness dependence of the macroscopic, transport diffusivity and the microscopic, self-diffusivity, which is reminiscent of diffusion in zeolites, where a similar difference arises due to adsorption effects and intermolecular interactions. Because of the dependence of the self-diffusivity on molecular residence times, self-diffusion may be roughness dependent, while transport diffusion is not. Detailed proofs are given. The differences become significant when the pore surface is rough down to molecular scales, as is the case, e.g., for many common sol–gel materials. Simulations are in good agreement with analytical calculations for several tested rough, fractal pore structures. These results are important for the interpretation of experimental diffusion measurements and for the study of diffusion-reaction processes in nanoporous catalysts with a rough internal surface.
231 citations
TL;DR: In this article, the bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time.
Abstract: Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.
120 citations
TL;DR: Both analytical and simulation results show a significant roughness dependence of self-diffusion in the Knudsen regime, whereas transport diffusion, on the other hand, is roughness independent, as the fluxes do not depend on the detailed residence time and molecular trajectory.
Abstract: The effect of surface roughness on Knudsen diffusion in nanoporous media is investigated by means of dynamic Monte Carlo simulations in three-dimensional rough fractal pores. These simulations yield new insight and explain a number of apparent inconsistencies by revealing a striking difference between the roughness dependence of transport diffusion and gradientless (self- or tracer) diffusion. Both analytical and simulation results show a significant roughness dependence of self-diffusion in the Knudsen regime. Transport diffusion, on the other hand, is roughness independent, as the fluxes do not depend on the detailed residence time and molecular trajectories.
113 citations
TL;DR: In this paper, high-k dielectric materials including zirconium oxide and hafnium oxide produced by atomic layer deposition have been evaluated for thermal stability using analyses derived from X-ray diffraction (XRD), Xray reflectometry (XRR), medium energy ion spectroscopy, high resolution transmission electron microscopy (HRTEM), tunneling atomic force microscopy, scanning electron microscopes, Auger electron spectroscope and secondary ion mass spectrography.
Abstract: High-k dielectric materials including zirconium oxide and hafnium oxide produced by atomic layer deposition have been evaluated for thermal stability. As-deposited samples have been compared with rapid thermal annealed samples over a range of source/drain dopant activation temperatures consistent with conventional complimentary metal oxide semiconductor polysilicon gate processes. Results of this initial investigation are presented utilizing analyses derived from X-ray diffraction (XRD), X-ray reflectometry (XRR), medium energy ion spectroscopy, high resolution transmission electron microscopy (HRTEM), tunneling atomic force microscopy, scanning electron microscopy, Auger electron spectroscopy and secondary ion mass spectroscopy. Changes in interface and surface roughness, percent crystallinity and phase identification for each material as a function of anneal temperature have been determined by XRD, XRR and HRTEM. Finally, high-k wet etch issues are presented relative to subsequent titanium silicide blanket film resistivity values.
63 citations