Extrinsic data compression method for double-binary turbo codes
20 May 2012-pp 1775-1778
TL;DR: This proposed compression method utilizes an operation in radix-4 single-binary turbo decoder and can simplify the integration of single and double- binary turbo decoders in hardware implementations and reduce one-third of extrinsic memory size.
Abstract: This paper presents an extrinsic data compression method for double-binary turbo codes. Frame and extrinsic data memory occupy more area in turbo decoder implementations with the frame size increasing. Besides, non-binary turbo codes have much more extrinsic memory usage than single-binary turbo codes. This proposed compression method utilizes an operation in radix-4 single-binary turbo decoder and also can simplify the integration of single and double-binary turbo decoders in hardware implementations. It can reduce one-third of extrinsic memory size, about 15% of total memory usage. Simulation results show that this method only causes 0.2dB performance loss when bit error rate is equal to 10−5 with slight hardware increment.
Citations
More filters
TL;DR: A reverse rate matching method is presented for LTE-Advanced turbo decoders that evaluates whether each code bit is punctured or not to reduce the meaningless accesses and more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high.
Abstract: In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%.
7 citations
Cites background from "Extrinsic data compression method f..."
...the border metric memory [10], and symbolic extrinsic information is compressed to achieve a smaller extrinsic information memory in double-binary turbo decoders [11], [12]....
[...]
01 Jan 2015
TL;DR: A reverse rate matching method is presented for LTE-Advanced turbo decoders that evaluates whether each code bit is punctured or not to reduce the meaningless accesses and more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high.
Abstract: In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%.
2 citations
References
More filters
Proceedings Article•
01 Jan 1993
7,742 citations
23 May 1993
TL;DR: In this article, a new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
Abstract: A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed. The turbo-code encoder is built using a parallel concatenation of two recursive systematic convolutional codes, and the associated decoder, using a feedback decoding rule, is implemented as P pipelined identical elementary decoders. >
5,963 citations
TL;DR: An intuitive shortcut to understanding the maximum a posteriori (MAP) decoder is presented based on an approximation to correspond to a dual-maxima computation combined with forward and backward recursions of Viterbi algorithm computations.
Abstract: An intuitive shortcut to understanding the maximum a posteriori (MAP) decoder is presented based on an approximation. This is shown to correspond to a dual-maxima computation combined with forward and backward recursions of Viterbi algorithm computations. The logarithmic version of the MAP algorithm can similarly be reduced to the same form by applying the same approximation. Conversely, if a correction term is added to the approximation, the exact MAP algorithm is recovered. It is also shown how the MAP decoder memory can be drastically reduced at the cost of a modest increase in processing speed.
757 citations
09 Oct 2009
TL;DR: A new hardware architecture that can share hardware resources for the two standards such as Mobile WiMAX and 3GPP-LTE is proposed, which mainly consists of eight retimed radix-4 soft-input soft-output (SISO) decoders to achieve high throughput and a dual-mode parallel hardware interleaver to support both almost regular permutations (ARP) and quadratic polynomial permutation (QPP) interleavers defined in the two Standards.
Abstract: This paper describes the energy-efficient implementation of a high performance parallel radix-4 turbo decoder, which is designed to support multiple fourth-generation (4G) wireless communication standards such as Mobile WiMAX and 3GPP-LTE We propose a new hardware architecture that can share hardware resources for the two standards It mainly consists of eight retimed radix-4 soft-input soft-output (SISO) decoders to achieve high throughput and a dual-mode parallel hardware interleaver to support both almost regular permutation (ARP) and quadratic polynomial permutation (QPP) interleavers defined in the two standards A prototype chip supporting both Mobile WiMAX and 3GPP-LTE standards is fabricated in a 013µm CMOS technology with eight metal layers The decoder core occupies 107mm2 and can exhibit a decoding rate of more than 100Mb/s with eight iterations while achieving an energy efficiency of 031nJ/bit/iter
85 citations
"Extrinsic data compression method f..." refers methods in this paper
...That method is also reformed as a table in [7]....
[...]
TL;DR: A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method to convert symbolic extrinsic information to bit-level information and vice versa, which reduces the total memory size by 20%.
Abstract: Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input-soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%.
36 citations