Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation
Citations
21 citations
Cites background or methods from "Extrinsic Information Memory Reduce..."
...The works proposed in [11], [14]–[16] are all aimed at reducing the footprint of the -MEM buffers at expense of reducing the error correcting capability of about 0....
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...While the works detailed in [11], [14], [15], and [16] deal with parallelism independent memories, this work, as [12] and [13], concerns parallelism dependent memories....
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...On the other hand, in [14] the same goal is achieved by using a pseudo-floating point representation, whereas in [15] a technique based on most significant bit (MSB) clipping combined with least significant bit (LSB) drop (at transmitter) and append (at receiver) is proposed....
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12 citations
Cites methods from "Extrinsic Information Memory Reduce..."
...In [15] an algorithm was proposed to decreases the necessary bit description width of the extrinsic information by employing a pseudo floating point representation....
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6 citations
6 citations
Cites methods from "Extrinsic Information Memory Reduce..."
...The adopted technique of traffic reduction offers in the best case a throughput improvement of more than 60 Mb/s and 40 Mb/s for binary and double-binary codes respectively....
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1 citations
Cites background or methods from "Extrinsic Information Memory Reduce..."
...Further studies have been performed to reduce the extrinsic information bit width by using adaptive quantization [Singh et al., 2008], pseudo-floating point representation [Park et al., 2008] and bit level representation [Kim & Park, 2009]....
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..., 2008], pseudo-floating point representation [Park et al., 2008] and bit level representation [Kim & Park, 2009]....
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References
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