Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
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TLDR
In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.Abstract:
Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.read more
Citations
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Journal ArticleDOI
Strained Si/SiGe n-channel MOSFETs: impact of cross-hatching on device performance
Sarah H. Olsen,Anthony O'Neill,D.J. Norris,A G Cullis,N. J. Woods,J. Zhang,Kristel Fobelets,H.A. Kemhadjian +7 more
TL;DR: In this paper, the performance of surface channel MOSFETs depends on the Si/SiO2 interface quality, and the results provide strong evidence that significantly enhanced performance of HNMOS surface channel devices is possible through optimization of epitaxial growth methods.
Proceedings ArticleDOI
Logic Performance of 40 nm InAs HEMTs
Dae-Hyun Kim,J.A. del Alamo +1 more
TL;DR: In this paper, the authors evaluated the logic performance of 40 nm InAs HEMTs and found that they exhibit excellent logic figures of merit and scalability at VDS = 0.5 V, such as DIBL = 80mV/V, S = 70 mV/dec, and fT = 475 GHz.
Proceedings ArticleDOI
Modeling of layout-dependent stress effect in CMOS design
TL;DR: A new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters, which significantly reduce the complexity in stress modeling and simulation.
Journal ArticleDOI
MC simulation of strained-Si MOSFET with full-band structure and quantum correction
Xiao-Feng Fan,Xin Wang,Xin Wang,B. Winstead,Leonard F. Register,Umberto Ravaioli,Sanjay K. Banerjee +6 more
TL;DR: The Monte Carlo University of Texas (MCUT) as discussed by the authors is a two-dimensional full-band Monte Carlo simulator that combines some of the best features of semiclassical MC device simulation including fullband structure and flexibility of scattering processes.
Patent
Strained semiconductor, devices and systems and methods of formation
Leonard Forbes,Paul A. Farrar +1 more
TL;DR: In this article, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region, and the volumes of the isolation region are adjusted to provide the channel region with a desired strain.
References
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Journal ArticleDOI
Thermal and Electrical Properties of Heavily Doped Ge‐Si Alloys up to 1300°K
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.