Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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20 Dec 2004
TL;DR: In this article, the authors present a review of the performance of n-channel MOSFETs and the challenges associated with their integration into conventional CMOS processes, and the optimum SiGe alloy composition for virtual substrate based devices is discussed.
Abstract: Strained Si/SiGe heterostructure MOS transistors offer great promise for nanoscale CMOS technology. This paper reviews these high performance devices and the challenges associated with their integration into conventional CMOS processes. Simulation results at a device and circuit level show that n-channel MOSFET performance can influence circuit speed to a greater extent than p-channel devices. Consequently the experimental work discussed is focused on recent progress in the optimisation of strained Si/SiGe n-channel MOSFETs. Simulation predicts that dual channel CMOS architectures offer the greatest performance advantages for both n- and p-channel MOSFETs. However, experimental evidence suggests that a single channel CMOS architecture may be a more pragmatic choice, given the material and processing complexities involved. The optimum SiGe alloy composition for virtual substrate based devices is discussed. Electron mobility is shown to peak in strained Si channels fabricated on relaxed Si0.75Ge0.25, yet wafer yield is compromised for virtual substrate compositions incorporating Ge contents above 15%. Optimum strained Si/SiGe device design is therefore shown to be highly dependent on the device parameter to be optimised, and specific processing conditions.
23 citations
06 Mar 2009-Compel-the International Journal for Computation and Mathematics in Electrical and Electronic Engineering
TL;DR: In this paper, an analytical drain current model for output characteristics of strained Si/SiGe bulk MOSFETs is presented, which correctly predicts the output characteristics, IDS−VGS characteristics, transconductance and output conductance of the strained Si and SiGe MOS FET.
Abstract: Purpose – The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.Design/methodology/approach – A physics‐based model for current output characteristics and transconductance of strained‐Si/SiGe bulk devices has been developed incorporating the impact of strain (in terms of equivalent Ge mole fraction), strained silicon thin film thickness, gate work function, channel length and other device parameters. The accuracy of the results obtained using this model is verified by comparing them with 2D device simulations.Findings – This model correctly predicts the output characteristics, IDS−VGS characteristics, transconductance and output conductance of the strained‐Si/SiGe MOSFET and demonstrates a significant enhancement in the drain current of the MOSFET with increasing strain in the strained‐Si thin film, i.e. with increasing equivalent Ge concentration in the SiGe bulk.Research limitations/implications – Can be implemented in a SPIC...
23 citations
Cites background from "Fabrication and analysis of deep su..."
...This effect can be attributed to an increase in the energy relaxation time with increasing strain (Rim et al., 2000): tw ¼ 0:1ps for x ¼ 0; tw ¼ 0:15ps for x ¼ 0:1; tw ¼ 0:2ps for x ¼ 0:2; ð11Þ where x is the Ge fraction in Si12xGex substrate....
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...This effect can be attributed to an increase in the energy relaxation time with increasing strain (Rim et al., 2000): tw 1⁄4 0:1ps for x 1⁄4 0; tw 1⁄4 0:15ps for x 1⁄4 0:1; tw 1⁄4 0:2ps for x 1⁄4 0:2; ð11Þ where x is the Ge fraction in Si12xGex substrate....
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TL;DR: In this paper, a novel thin virtual substrate aimed at reducing self-heating effects is investigated, which provides further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates.
23 citations
TL;DR: In this paper, the authors used density functional theory calculations to investigate the stress dependence of boron (B) and arsenic (As) diffusion including vacancy (V) and interstitial (I) mechanisms under arbitrary stress/strain states.
Abstract: Understanding changes in dopant diffusion under strain is critical for controlling junction profiles in current and future very large scale integrated technology due to expanding use of large strains to enhance channel mobility. We use density functional theory calculations to investigate the stress dependence of boron (B) and arsenic (As) diffusion including vacancy (V) and interstitial (I) mechanisms under arbitrary stress/strain states. We have also analyzed the effects of stress on I and V diffusion with resulting impact on transient enhanced diffusion and coupled diffusion. For B diffusion, which is primarily mediated by I, we find greatly enhanced diffusion under tensile stress. Due to low symmetry of calculated transition state, we predict strongly anisotropic diffusion under anisotropic strain, with the strongest effects in direction of strain. This has a major impact on control of lateral junction abruptness as seen in two-dimensional simulations. The predicted behavior is consistent with combine...
22 citations
TL;DR: On-state and off-state performance of Si-SiGe n-channel MOSFETs have been investigated as a function of SiGe virtual substrate alloy composition in this article.
Abstract: On-state and off-state performance of strained-Si-SiGe n-channel MOSFETs have been investigated as a function of SiGe virtual substrate alloy composition Performance gains in terms of on-state drain current and maximum transconductance of up to 220% are demonstrated for strained-Si-SiGe devices compared with Si controls Device performance is found to peak using a virtual substrate composition of Si/sub 075/Ge/sub 025/ MOSFET fabrication used high thermal budget processing and good gate oxide quality has been maintained for virtual substrates having Ge compositions up to 30% Off-state characteristics are found to be more sensitive to strain relaxation than on-state characteristics
22 citations
References
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IBM1
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations