Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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TL;DR: In this article, the authors investigated the impact of strain-induced mobility enhancement on n-and p-channel, metal-oxide-semiconductor field effect transistors at five temperatures ranging from 296 to 367 K.
Abstract: Device characteristics and analyses are reported for strained silicon n- and p-channel, metal-oxide-semiconductor field-effect transistors at five temperatures ranging from 296 to 367 K. Both partially depleted and bulk architectures were investigated. The devices were fabricated commercially on homogeneous silicon-based substrates and strain was applied mechanically after fabrication. Tensile uniaxial strain was applied within the elastic region using a back-end process. It was applied either parallel to or perpendicular to the carrier transport direction. Tensile biaxial strain was also induced in selected samples by using high thermal expansion Al substrates. Samples mounted on Al substrates experienced increasing strain as the temperature was raised. The structures were relaxed and characterized under steady-state conditions at each temperature level. No degradation of strain-induced mobility enhancement was observed due to increased temperature. We conclude that a reduction in average effective mass ...
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02 Jun 2008
TL;DR: In this paper, a combination of two statistical tools, namely Design of Experiments (DoE) and Response Surface Modeling (RSM), is used to identify and model those process parameters whose variation which will impact most on the performance of a circuit.
Abstract: For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently it is no longer feasible to optimise the process during the product lifetime resulting in an increase in parametric yield loss. This paper describes the use a combination of two statistical tools namely Design of Experiments (DoE) and Response Surface Modelling (RSM) which permit the identification and modelling of those process parameters whose variation which will impact most on the performance of a circuit. The efficiency of this approach, compared to using a Monte Carlo analysis, is demonstrated with respect to a Mutual Exclusion Element (MUTEX) which is used extensively in synchronisers where process variations can have considerable impact on circuit performance. To obtain the same modelling accuracy, the Monte Carlo approach would require large number of simulations compared to nine using the DoE scheme with the low computational overhead. This method can be used by semiconductor manufacturers and design house alike to bridge the gap between manufacture and design.
13 citations
TL;DR: In this paper, an analytical model of the threshold voltage and drain current for gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field effect transistors (MOSFETs) was proposed.
Abstract: Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.
13 citations
TL;DR: In this paper, real-space maps of strain within silicon-on-insulator (SOI) features induced by adjacent, embedded shallow-trench-isolation (STI) SiO2 regions were obtained using x-ray microbeam diffraction.
Abstract: Real-space maps of strain within silicon-on-insulator (SOI) features induced by adjacent, embedded shallow-trench-isolation (STI) SiO2 regions were obtained using x-ray microbeam diffraction. The quantitative strain mapping indicated that the SOI strain was largest at the SOI/STI interface and decreased as a function of distance from this interface. An out-of-plane residual strain of approximately −31μe was observed in the blanket regions of the SOI. A comparison of the depth-averaged strain distributions to the strain profiles calculated from an Eshelby inclusion model indicated an equivalent eigenstrain of −0.55% in the STI regions acting on the SOI features.
13 citations
TL;DR: In this paper, the authors focus on strained Si layers on insulator and highlight the potential of wafer bonding and layer transfer techniques to increase the charge carrier mobility of silicon-on-insulator (SOI) architectures.
Abstract: Silicon-on-insulator (SOI) is today the substrate of choice for several applications, including high performance and low power ICs. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement to meet the performance needs of the 65 nm technology nodes and beyond. One possible option is to increase transistor channel mobility through local strain engineering via stressors like nitride layers or epitaxial SiGe source/drain pockets. This is the so-called “local strain” or “process-induced strain” approach. Another solution is to induce a MOSFET mobility increase via substrate engineering, which presents the advantage of being independent of transistor geometry. If necessary, the two approaches can be combined. The attractiveness of wafer level-based solutions is largely due to their compatibility with standard CMOS integration processes and architectures. Among the different substrate level options investigated by the industry, we will focus here on strained Si layers on insulator. Different wafer manufacturing techniques will be considered, and the potential of wafer bonding and layer transfer techniques will be highlighted.
13 citations
References
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TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations