Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Abstract: Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.
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TL;DR: In this paper, the electrothermal properties of a strain-Si MOSFET in the presence of high electric fields were investigated using full-band Monte Carlo device simulation.
Abstract: The electrothermal characteristics of strained-Si MOSFETs, operating in the high-current regime, have been studied using device simulation. The phonon mean-free-path of strained-Si devices in the presence of high electric fields is determined, based on fullband Monte Carlo device simulation. Strained-Si nMOS devices have higher bipolar current gain and impact ionization rates compared to bulk-Si nMOS devices due to the smaller energy bandgap and longer phonon mean-free-path. Even though strained-Si devices have self-heating problems due to the lower thermal conductivity of the buried SiGe layer, the devices can be used beneficially for electrostatic discharge protection devices to achieve lower holding voltage (V/sub h/) and higher second breakdown triggering current (I/sub t2/), compared to those of bulk-Si devices, owing to the high bipolar current gain and current uniformity.
12 citations
Cites background from "Fabrication and analysis of deep su..."
...In the [1] the energy relaxation time was increased by roughly a factor of two from the bulk-Si value....
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...Strained-silicon has drawn attention due to its enhanced carrier transport and its compatibility with mainstream Si CMOS processing [1]....
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TL;DR: A temperature dependent model for the threshold voltage Vt and subthreshold slope S of strained-Si channel MOSFETs is presented and Vt is found to be sensitive to strain while S is weakly dependent on strain.
12 citations
TL;DR: In this paper, depth and in-plane profiling of strain, Ge composition, and defects in strained-Si ∕Si 1−xGex∕Si heterostructures using micro-Raman imaging is reported.
Abstract: We have reported depth and in-plane profiling of strain, Ge composition, and defects in strained-Si∕Si1−xGex∕Si heterostructures using micro-Raman imaging. Raman profiling in the depth direction was carried out with a depth resolution of ∼15nm using a small-angle beveled sample and ultraviolet (UV) excitation. Depth profiles of the Ge composition and Raman bandwidth clearly show that the defect density depends strongly on the Ge-grading rate in a compositionally graded Si1−xGex layer. The in-plane strain variation at a given depth in each layer has been evaluated. The in-plane strain variations in the Si1−xGex are closely related to clustering of misfit dislocations in the graded Si1−xGex layer. For the top strained-Si layer, two-dimensional UV-Raman images of the frequency and bandwidth of the Si band reveal that film crystallinity is correlated with the magnitude of in-plane strain. The close correlation between the frequency and bandwidth is attributed to inhomogeneous strain fields associated with mis...
12 citations
TL;DR: In this article, the measured performance of sub-micron Si:SiGe Schottky gated HFETs compared to Si nMOSFETs is compared to allow an up-to-date comparison between Si and strained-Si FETs.
Abstract: The measured performance of sub-micron Si:SiGe Schottky gated HFETs is compared to Si nMOSFETs. To allow an up-to-date comparison between Si and strained-Si FETs, the different device types have been studied in their respective technologies. RF performance as given by the cut-off and maximum oscillation frequency is given as a function of input power. The evaluation highlights the current immaturity of the Si:SiGe technologies, where an average HFET shows a maximum transconductance of ∼300 mS/mm and cut-off frequency ∼60 GHz, while the new generation Si nMOS is reaching 1300 mS/mm and 120 GHz respectively. The comparison shows that the strength of the HFETs lies in low power operation (
12 citations
Additional excerpts
...During the last 10 years, research papers have been published on the possible improvements of SiGe FETs with strained Si channels, both in a buried channel [1,2] and a surface channel configuration [3,4], and compared them to conventional Si nFETs which are traditionally fabricated in the same processing run....
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01 Dec 2017
TL;DR: Parameters like the trans-conductance, drain conductance, trans- conductance generation factor, total gate capacitance, cut-off frequency, gain frequency product(GFP) for analog and RF performance, and for digital application noise margin and propagation delay have been extracted.
Abstract: This paper presents TCAD simulation of Triple gate Step Fin FinFET (SF-FinEFT) and Step Drain FinFET(SD-FinFET) field effect transistor The electrical characteristics of the devices are compared with conventional Fin-FET(cFinFET/FinFET) Various performance parameter like ON current Ion, leakage current Ioff, Ion/Ioff ratio, sub-threshold slope, DIBL have been observed Also to check the device functionality in Analog, RF and Digital applications a comparative study of various parameters has been done between the proposed devices and conventional FinFET We have used strained silicon as channel material for all the devices As the number of transistors per square area on a chip keeps on increasing, the performance metrics for a planar MOSFET degrades and hence it faces various challenges in nano-meter regime The need for a new device technology to control the unavoidable challenges was felt hence a 3-D Multi-gate transistor have emerged These newer 3-D devices showed better performance in the nano meter regime This paper analyzes parameters like the trans-conductance(gm), drain conductance (gd), trans-conductance generation factor, total gate capacitance (Cgg), cut-off frequency (ft), gain frequency product(GFP) for analog and RF performance For digital application noise margin and propagation delay have been extracted
12 citations
References
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TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this paper, the thermal resistivity, Seebeck coefficient, electrical resistivity and Hall mobility of GeSi alloys have been measured throughout the GeSi alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in range 300°-1300°K.
Abstract: The thermal resistivity, Seebeck coefficient, electrical resistivity, and Hall mobility of Ge‐Si alloys have been measured throughout the Ge‐Si alloy system as functions of impurity concentration in the range 2×1018−4×1020cm−3, and of temperature in the range 300°–1300°K. A qualitative interpretation of these properties is given. For power conversion, boron and phosphorus were found to be useful p‐type and n‐type impurities, respectively, because of their high solid solubilities. At 1200°K, the maximum values of the dimensionless figure of merit zT were 0.8 for p‐type Ge0.15‐Si0.85 alloy doped to 2.1×1020cm−3 holes, and 1.0 for n‐type Ge0.15‐Si0.85 alloy doped to 2.7×1020cm−3 electrons. The maximum over‐all efficiency of a stable generator operating between 300°–1200°K, using the best p‐type and n‐type materials was computed to be 10%.
556 citations
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Abstract: The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...
454 citations
TL;DR: In this paper, the authors developed a technique for measuring the thermal conductivity of silicon-on-insulator (SOI) transistors and provided data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology.
Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
358 citations